A kind of sic MOSFET gate oxide layer annealing method

Abstract

The invention relates to a SiC MOSFET gate oxide layer annealing method. The method comprises the following steps: preparing a SiC epitaxial wafer; growing a SiO2 gate oxide layer on the SiC epitaxialwafer; and performing annealing processing on the SiO2 gate oxide layer under an environment condition of inert gas and Cl2 mixed gas. The SiO2 gate oxide layer of the SiC MOSFET device is annealed by using the inert gas and the Cl2 mixed gas, and the critical breakdown electric field capacity of the SiO2 gate oxide layer in the SiC MOSFET device is improved.

Description

technical field [0001] The invention belongs to the field of SiC MOSFET devices, and in particular relates to an annealing method for a SiC MOSFET gate oxide layer. Background technique [0002] As a third-generation semiconductor material, SiC has the advantages of wide band gap, high thermal conductivity, and high breakdown field strength. It is suitable for making high-temperature, high-power, high-temperature, high-frequency, and radiation-resistant devices. Therefore, SiC is widely used in a semiconductor field effect transistor (Metal-oxide Semiconductor Field Effect Transistor, MOSFET for short). [0003] In SiC MOSFET, due to the SiO 2 Lattice mismatch with SiC material, in SiO 2 Gate Oxide SiO 2 A large number of trap charges such as dangling bonds, carbon clusters and oxygen vacancies will be generated in the interface and the SiC interface of the SiC epitaxial wafer, which will affect the performance of the device. Currently reduced SiO 2 The way to trap char...

AI Technical Summary

Problems solved by technology

[0004] But in SiC MOSFET, at high temperature growing SiO 2 gate oxide process, SiO 2 Gate Oxide SiO 2 A large amount of oxygen vacancy trap charges will be generated in the interface and the SiC interface of the SiC epitaxial wafer, which will reduce the SiO in SiC MOSFET devices. 2 Critical breakdown electric field capability of gate oxide layer

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