Method for manufacturing silicon wafer
A manufacturing method and silicon wafer technology, applied in the field of silicon wafer manufacturing, can solve problems such as the impact of device yield, device characteristic degradation, and device leakage current that cannot be ignored, and achieve the effect of reducing RIE defects
Active Publication Date: 2019-03-15
SUMCO CORP
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Problems solved by technology
[0013]
However, the potential RIE defects in the wafer are generated when heat treatment is performed under specific conditions, but the impact on the yield of the device cannot be ignored
For example, when OSF is formed on the surface of the wafer, it becomes a cause of leakage current and degrades device characteristics
And, if P
V
Oxygen precipitation nuclei in the region generate oxygen precipitation during heat treatment in the device manufacturing process, and cause the oxygen precipitation to remain in the active layer of the device component, which may cause leakage current in the device
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[0092] Next, the present invention will be described in more detail through examples, but the present invention is not limited to these examples.
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This method for manufacturing a silicon wafer includes: a growing step for growing, by means of a Czochralski method, a silicon single crystal not containing crystal-originated particles (COP) and dislocation clusters; an oxidation-induced stacking fault (OSF) evaluation step for evaluating the OSF occurrence status of an evaluation wafer obtained from the silicon single crystal; and a heat treatment step for performing, under the condition of 1,310 DEG C or higher, rapid thermal oxidation (RTO) treatment with respect to a silicon wafer obtained from the same silicon single crystal from whichthe evaluation wafer has been obtained, in the cases where the evaluation wafer has an OSF, and performing the RTO treatment under the condition below 1,310 DEG C with respect to the silicon wafer inthe cases where the evaluation wafer does not have the OSF.
Description
technical field [0001] The invention relates to a method for manufacturing a silicon wafer. Background technique [0002] A silicon wafer (hereinafter, sometimes referred to as "wafer") used as a substrate of a semiconductor device is usually cut out and polished from single crystal silicon grown by the Czochralski method (hereinafter, sometimes referred to as "CZ method") Wait for the process to manufacture. In crystals grown by the CZ method, crystal defects called native defects sometimes occur. [0003] figure 1 It is a longitudinal cross-sectional view of a pulled silicon single crystal and schematically shows an example of the relationship between defect distribution and V / G. V is the pulling speed of the single crystal silicon, and G is the temperature gradient in the growth direction of the single crystal silicon immediately after pulling. [0004] The temperature gradient G is considered to be substantially constant from the thermal characteristics of the therma...
Claims
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Patent Timeline
Login to View More IPC IPC(8): H01L21/324C30B29/06C30B33/02H01L21/322
CPCC30B29/06C30B33/02H01L21/322H01L21/324H01L22/12H01L21/3225H01L22/20C30B15/203H01L22/14C30B33/00H01L21/02002
Inventor 松山博行
Owner SUMCO CORP
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