TSV array temperature optimization method based on an orthogonal test

A technology of orthogonal test and optimization method, applied in the field of microelectronics, can solve the problems of low accuracy, large workload, poor general applicability, etc., to improve efficiency and accuracy, reduce required time, avoid comprehensive testing and The effect of random error

Pending Publication Date: 2019-03-26
XIDIAN UNIV
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Problems solved by technology

Among them, the method based on the calculation of equivalent thermal conductivity has poor universal applicability. For different actual circuit structures, it is necessary to re-deduce the formula, and the workload is large, resulting in

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  • TSV array temperature optimization method based on an orthogonal test
  • TSV array temperature optimization method based on an orthogonal test
  • TSV array temperature optimization method based on an orthogonal test

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[0023] The embodiments and effects of the present invention will be described in further detail below with reference to the accompanying drawings.

[0024] Reference figure 1 , The present invention is based on the orthogonal experiment of the TSV array temperature optimization method of through silicon vias, and the implementation steps are as follows:

[0025] Step 1. Set the factors that affect the temperature of the TSV array of through silicon vias.

[0026] The setting factors include: hole category C, radius R, spacing D, filling material M tsv , Arrangement method S, insulating layer thickness H and insulating layer material M iso .

[0027] Step 2. Select the key factors affecting the temperature of TSV arrays.

[0028] At least three factors are selected as the key factors from the factors affecting the temperature of the TSV array of through silicon vias. The number of key factors selected in this example is four, namely the radius R of the TSV, the spacing D of the TSV, th...

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Abstract

The invention discloses a TSV (Through Silicon Via) array temperature optimization method based on an orthogonal test, which mainly overcomes the defects of low efficiency and low precision of the existing three-dimensional integrated circuit temperature optimization technology, and comprises the following implementation steps of: setting a factor influencing the temperature of a TSV array; Selecting at least three factors as key factors; Selecting parameters for each key factor; Generating an orthogonal test table according to the selected factors and parameters; Establishing a through-silicon-via geometric model by utilizing finite element simulation software, arranging a test according to an orthogonal test table, and adding a result into the orthogonal test table; And determining the primary and secondary sequence of the temperature influenced by each factor, and designing an optimal scheme for reducing the temperature of the through-silicon-via array. Based on orthogonal tests andfinite element simulation, a test result with the precision higher than that of a traversal test can be obtained within the limited number of tests, the calculation time is greatly saved, large-scaledata processing is avoided, the temperature optimization efficiency and precision of the TSV array are improved, and the method can be used for designing a three-dimensional integrated circuit.

Description

technical field [0001] The invention relates to the technical field of microelectronics, in particular to a method for optimizing the temperature of a through-silicon via TSV array, which can be used in the design of a three-dimensional integrated circuit. Background technique [0002] As the feature size of the device gradually approaches the physical limit, it becomes more and more difficult to increase the integration level of the chip. The 3D integrated circuit based on through-silicon vias can provide vertical interconnection between chips, which greatly reduces the global interconnection length, breaks through the development bottleneck of two-dimensional integrated circuit interconnection delay and power consumption, and becomes a new technology for realizing high-density integration of systems. one of the key technologies. Although three-dimensional integration technology has many advantages, the chip temperature rise caused by its high device integration and high p...

Claims

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Application Information

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IPC IPC(8): G06F17/50
CPCG06F30/39G06F30/23Y02D10/00
Inventor 董刚罗心月杨银堂
Owner XIDIAN UNIV
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