Three-dimensional active heat-dissipation packaging structure of embedded micro channel and manufacturing process thereof

Abstract

The invention, which belongs to the technical field of integrated circuit packaging, relates to a three-dimensional active heat-dissipation packaging structure of an embedded micro channel and a manufacturing process thereof. The three-dimensional active heat-dissipation packaging structure comprises a three-dimensional packaging structure. A micro channel chip structure unit is arranged at the top layer of the three-dimensional packaging structure and includes an IC chip having an embedded micro flow structure and a micro channel cover plate. A two-dimensional heterogeneous integrated structural unit is arranged at the bottom layer of the three-dimensional packaging structure and includes a TSV adapter board connected with a bottom filling layer through array salient points and an IC chip; the micro channel chip structure unit and the two-dimensional heterogeneous integrated structural unit are connected with the bottom filling layer through the array salient points; and then packaging with an embedded micro channel substrate and a housing is carried out to form a three-dimensional active heat-dissipation packaging structure. Therefore, the inter-layer thermal resistance of the three-dimensional packaging system is reduced substantially; the heat dissipation capability of the circuit is improved effectively; and the high-density and high-performance three-dimensional system-level packaging is enhanced and the safety and reliability are high.

Description

technical field [0001] The invention relates to a three-dimensional packaging structure, in particular to a three-dimensional active heat dissipation packaging structure with embedded micro-channels and a manufacturing process thereof, belonging to the technical field of integrated circuit packaging. Background technique [0002] With the increase of integration, power consumption and size reduction of modern electronic chips, the rapidly increasing heat generation of chip systems has become a major challenge in the development and application of advanced electronic chip systems. Generally, the failure rate of components increases exponentially with the increase of device temperature, and the reliability of the device decreases by 5% for every 1°C increase in the level of 70-80°C. Especially in the three-dimensional packaging system, the problem of thermal management cannot be ignored, because: (1) The three-dimensional packaging system often integrates multiple chips, the n...

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Problems solved by technology

Generally, the failure rate of components increases exponentially with the increase of device temperature, and the reliability of the device decreases by 5% for every 1°C increase at the level of 70-80°C.

Especially in the three-dimensional packaging system, the problem of thermal management cannot be ignored, because: (1) The three-dimensional packaging system often integrates multiple chips, the number of transistors is large, and the heat generation is large, but the overall packaging area does not increase accordingly. increase, so it has a higher heat generation density; (2) the chip is packaged in a three-dimensional stack, which is not conducive to heat dissipation, and the heat dissipation of the chip at the bottom and middle of the stack will be more difficult; (3) for the three-dimensional assembly structure, The copper conductor part is surrounded by insulating layer, chip, substrate and other structures, making it difficult to dissipate the heat generated by the chip

These factors cause the temperature of the chip to increase rapidly

[0003] Conventional heat dissipation methods mainly include heat conduction, convection, micro-spray cooling, radiation and phase change refrigeration, etc., but the volume and efficiency of equipment corresponding to these heat dissipation methods are not satisfactory

Especially when the power density of the system is higher than 100W / cm 2 These thermal management methods simply cannot be applied when

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