A multi-level low-latency interconnect structure based on axi protocol

Abstract

The invention relates to a multi-level low-delay interconnection structure based on an AXI protocol. The high-throughput low-delay on-chip bus interconnection unit comprises a high-throughput low-delay on-chip bus interconnection unit and an inter-core bus interconnection unit, The system comprises a plurality of conversion bridges including an AMBA multi-level interconnection structure, an AMBA slave device interface, an AMBA master device interface, an AXI2AHB bridge, an AXI2AXI bridge, an AHB2APB bridge, an AHBLite2AXI bridge and the like. Wherein the on-chip bus is a multi-level low-delaybus interconnection unit responsible for communication between a kernel and a system peripheral and high-performance acceleration unit. The inter-core bus is a high throughput, low latency bus interconnect unit that processes inter-core interconnect communications. Through a timeout management mechanism, technologies such as virtual multichannel multiplexing design and the like are added, a multi-layer bus interconnection structure is utilized, the data transmission throughput rate is effectively improved, the transmission delay is reduced, and meanwhile the performance such as reliability isconsidered.

Description

technical field [0001] The invention relates to an interconnection structure, in particular to a multi-level low-delay interconnection structure based on the AXI protocol, and belongs to the field of integrated circuit multi-core interconnection architecture design. Background technique [0002] With the continuous development of integrated circuit technology, in order to achieve higher processing performance and efficiency, multi-core processors have become the mainstream design. The design of multi-core processors is based on IP core multiplexing technology, so the method of interconnecting IP cores will increasingly affect performance indicators such as the data throughput rate of the processor. At present, there are a variety of IP core interconnection specifications in the world, including IBM's CoreConnect bus, ARM's AMBA (Advanced Microcontroller Bus Architecture), SilicoreCorp's Wishbone, Altera's Avalon bus, and MIPS' ECTM Interface. [0003] Among them, AXI is the...

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Problems solved by technology

[0004] In the design process of complex multi-core processors, the interconnection and communication between multiple modules such as cores, cores and acceleration units, cores and peripherals are involved, and data consistency and interconnection buses are involved. A series of problems such as low data throughput

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