Test structure, its method of manufacture and method of its application
A technology for testing structures and manufacturing methods, applied to semiconductor devices, electrical components, circuits, etc., can solve problems such as waste of resources, and achieve resource saving and low cost effects
Active Publication Date: 2021-04-13
SHANGHAI HUALI INTEGRATED CIRCUIT CORP
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Problems solved by technology
The conventional method is to design well doping and non-doping on different wafers, but this method will be affected by differences between different wafers, and on the other hand, it will also cause waste of resources
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[0024] The technical solutions in the present invention will be clearly and completely described below in conjunction with the accompanying drawings. Apparently, the described embodiments are part of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.
[0025] An embodiment of the present invention provides a test structure for evaluating the effect of substrate well doping on device characteristics. The test structure of the present invention includes multiple groups of semiconductor devices, wherein the specific structure of each group of semiconductor devices can be found in figure 2 , figure 2 It is a schematic diagram of a group of semiconductor devices in the test structure of an embodiment of the present invention, such as figure 2 As shown, the group...
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The present invention relates to a kind of test structure, relates to semiconductor integrated circuit, by simultaneously manufacturing multiple groups of NMOS with P well, PMOS with N well, PMOS without well and NMOS semiconductor device without well, and each group of semiconductor devices The channel lengths are different, and test the threshold voltage of at least one group of semiconductor devices with well-doped devices and without well-doped devices to obtain a threshold voltage database, and analyze the threshold voltage database to obtain the well-doped threshold value The influence of voltage; extract the channel carrier mobility of each group of devices with well doping and the channel carrier mobility of devices without well doping, obtain the channel carrier mobility database, and analyze the channel carrier mobility. The carrier mobility database obtains the effect of well doping on the carrier mobility of the channel, so that the effect of well doping on the device threshold voltage (Vt) and the carrier mobility (Ion / Ioff) in the channel can be evaluated, And the cost is low, saving resources.
Description
technical field [0001] The invention relates to a semiconductor integrated circuit, in particular to a test structure, its manufacturing method and its application method. Background technique [0002] In semiconductor integrated circuits, with the development of semiconductor technology, due to the requirements of device size reduction and the limitation of photolithography technology, the development of bulk silicon CMOS has encountered a bottleneck after reaching 22nm, and the MOSFET on the fully depleted insulating layer ( FDSOI) has become a current research hotspot because of its low operating voltage and high radio frequency characteristics. Traditional bulk silicon achieves multiple threshold voltages (Vt) through channel doping and channel length design. Channel doping will cause device leakage and threshold voltage Vt fluctuations due to RDF (random dopants fluctuation). serious. The channel doping concentration of FDSOI is very low, and Halo ion implantation is ...
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IPC IPC(8): H01L27/085
CPCH01L27/085
Inventor 汪雪娇徐翠芹刘巍王昌锋陈蓓
Owner SHANGHAI HUALI INTEGRATED CIRCUIT CORP