Semiconductor integrated circuit device

Abstract

The present invention provides a semiconductor integrated circuit device, using a nanowire FET, that has a layout configuration effective in facilitating easy manufacturing. A standard cell (C2) having no logical function is disposed adjacent to a standard cell (C1) having a logical function. The standard cell (C1) has nanowire FETs (P11, P12, N11, N12) having nanowires (11, 12, 13, 14) and pads (21, 22, 23, 24, 25, 26). The standard cell (C2) has dummy pads (51, 52, 53, 54) that are pads having no contribution to a logical function of the circuit.

Description

technical field [0001] The present disclosure relates to a semiconductor integrated circuit device including a standard cell (hereinafter, sometimes simply referred to as a cell) using a nanowire FET (Field Effect Transistor: Field Effect Transistor). Background technique [0002] It is known that there is a standard cell method as a method of forming a semiconductor integrated circuit on a semiconductor substrate. The standard cell method refers to the following method, that is, the basic cells with specific logic functions (such as inverters, latches, flip-flops, full adders, etc.) are prepared as standard cells in advance, and then multiple standard cells are arranged On the semiconductor substrate, these standard cells are connected by wiring, which is a way to design an LSI chip. [0003] Transistors, which are the basic components of LSI, have achieved increased integration, reduced operating voltage, and increased operating speed by reducing gate length (scaling, pro...

AI Technical Summary

Problems solved by technology

However, in recent years, there has been a problem that excessive scaling down causes significant increases in off-current and power consumption

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