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Semiconductor integrated circuit device

A technology of integrated circuits and semiconductors, which is applied in semiconductor devices, circuits, semiconductor/solid-state device manufacturing, etc., and can solve problems such as increased power consumption

Inactive Publication Date: 2020-07-28
SOCIONEXT INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, in recent years, there has been a problem that excessive scaling down causes off-current, which in turn causes a significant increase in power consumption

Method used

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  • Semiconductor integrated circuit device
  • Semiconductor integrated circuit device
  • Semiconductor integrated circuit device

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Experimental program
Comparison scheme
Effect test

no. 1 approach

[0060] Figure 1 ~ Figure 3 An example of the layout structure of the unit related to the first embodiment is shown, figure 1 Is a top view, figure 2 (a), figure 2 (b) is a top view of different layers, image 3 (a)~ image 3 (e) is a sectional view. in particular, figure 2 (a) shows the VNW FET and the layers below it, figure 2 (b) shows the layers above the VNW FET. image 3 (a)~ image 3 (c) When looking down figure 1 A cross-sectional view taken along the longitudinal direction at image 3 (d)~ image 3 (e) When looking down figure 1 A cross-sectional view taken along the transverse direction, image 3 (a) is a section taken along the line X1-X1', image 3 (b) is a section taken along the line X2-X2’, image 3 (c) is the section taken along the line X3-X3’, image 3 (d) is a section taken along the line Y1-Y1', image 3 (e) is a section taken along the line Y2-Y2'.

[0061] Figure 4 Yes Figure 1 ~ Figure 3 Circuit diagram of the unit shown. Such as Figure 4 As shown, F...

no. 2 approach

[0091] Figure 9~Figure 11 An example of the layout structure of the unit related to the second embodiment is shown, Picture 9 Is a top view, Picture 10 (a), Picture 10 (b) is a top view of different layers, Picture 11 (a)~ Picture 11 (e) is a sectional view. in particular, Picture 10 (a) shows the VNWFET and the layers below it, Picture 10 (b) shows the layers above the VNW FET. Picture 11 (a)~ Picture 11 (c) When looking down Picture 9 A cross-sectional view taken along the longitudinal direction at Picture 11 (d)~ Picture 11 (e) When looking down Picture 9 A cross-sectional view taken along the transverse direction, Picture 11 (a) is a section taken along the line X1-X1', Picture 11 (b) is a section taken along the line X2-X2’, Picture 11 (c) is the section taken along the line X3-X3’, Picture 11 (d) is a section taken along the line Y1-Y1', Picture 11 (e) is a section taken along the line Y2-Y2'. Figure 9~Figure 11 The unit shown implements Figure 5 2 inp...

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Abstract

Provided is a layout structure of a standard cell using vertical nanowire FETs (VNW FET). According to the present invention, a P-type transistor region (Pch) in which VNW FETs are formed and an N-type transistor region (Nch) in which VNW FETs are formed are provided between a power supply line (VDD) and a power supply line (VSS). A local line (37) is disposed across the P-type transistor region (Pch) and the N-type transistor region (Nch). Top electrodes of transistors (P3, N3), which are dummy VNW FETS, are connected to the local line (37).

Description

Technical field [0001] The present disclosure relates to a semiconductor integrated circuit device, which includes a standard cell including a vertical nanowire (VNW: Vertical Nanowire) FET (Field Effect Transistor, field effect transistor). Background technique [0002] The standard cell method is a known method of forming semiconductor integrated circuits on a semiconductor substrate. The standard cell method refers to the following method, that is, the basic cells with specific logic functions (such as inverters, latches, flip-flops, full adders, etc.) are prepared as standard cells in advance, and then multiple standard cells Arrange on the semiconductor substrate, and then use wiring to connect these standard cells, so as to design the LSI chip. [0003] The basic constituent element of the LSI, the transistor, has achieved an increase in integration, a decrease in operating voltage, and an increase in operating speed by reducing the gate length (scaling). However, in recent...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/82H01L21/822H01L21/8234H01L27/04H01L27/088
CPCH01L27/092H01L21/823885H01L21/823871H01L27/0207H01L27/11807H01L29/66439H01L29/7827H01L29/0676H01L29/41741B82Y10/00H01L29/775H01L29/41725H01L21/76895H01L23/5286
Inventor 岩堀淳司
Owner SOCIONEXT INC
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