high-bandwidth MIPI data processing interface circuit

Abstract

A high-bandwidth MIPI data processing interface circuit comprises a four-channel data input module, a data processing interface module and an MIPI transmission module. According to the invention, an optimized pixel data processing mode is adopted to reduce INPUT CLOCK FREQUENCY. Pixel data is packed inside the traditional MIPI interface. Multiple physical channel data is merged and data is buffered into the high-bandwidth MIPI data processing interface circuit for pre-processing. Pixel data is the MIPI is not necessarily packed and buffered. A user needs to send according to time sequence, thereby making pixel data easier and more efficient.

Description

technical field [0001] The invention relates to the field of digital circuit design, in particular to a MIPI data processing interface circuit with high bandwidth. Background technique [0002] The MIPI alliance is the Mobile Industry Processor Interface (MIPI for short) alliance. MIPI (Mobile Industry Processor Interface) is an open standard and a specification initiated by the MIPI Alliance for mobile application processors. [0003] In other words, MIPI is not just an alliance but also the name of a set of interface protocol specifications. It governs different working groups (Work Group) to meet the different needs of each subsystem of the mobile terminal. Different working groups are responsible for formulating specific protocols, and define a set of internal interface standards for mobile devices for different hardware devices, such as camera serial interface CSI, display serial interface DSI, radio frequency interface DigRF, etc. [0004] It is clear to those skill...

AI Technical Summary

Problems solved by technology

For the data type of RAW8, the input clock frequency must reach 750Mhz; such a high clock frequency is difficult to achieve for many chip processes

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