SOC chip field programmable logic array prototype integration method and system

Abstract

The invention relates to an SOC chip field programmable logic array prototype integration method and system. The method comprises the following steps that S1, judging whether an engineering folder isestablished or not; S2, establishing an engineering folder according to the parameterized device selection and the engineering directory; S3, judging whether an old engineering folder exists or not; S4, establishing a new engineering folder; S5, performing backup according to the time of the current engineering folder; S6, judging whether the engineering folder is integrated or arranged for wiring; S7, starting a comprehensive tool, and calling a syn.tcl file; S8, judging whether the integrated engineering folder is subjected to layout wiring or not; S9, starting a layout wiring tool, and calling a pr.tcl file; And S10, outputting various reports. The method can be compatible with a multi-field programmable logic array prototype hardware environment, achieves calling of different tools, ishigh in automation degree, good in usability, good in expansibility and easy to maintain, and greatly improves the efficiency of the field programmable logic array prototype.

Description

technical field [0001] The invention relates to the technical field of solid-state storage, and more specifically refers to a method and system for SOC chip field programmable logic array prototype synthesis. Background technique [0002] For SSD-Solid State Drives (Solid State Drives) SOC chip verification, due to the limitations of EDA verification, FPGA propotyping verification is generally used together (emulator (hardware acceleration emulator) is also used if conditions permit). In programming logic array prototype verification), there are generally multiple FPGA propotying (field programmable logic array prototype) hardware platforms, and frequent iterations. Using traditional methods, maintenance is difficult, low efficiency, and low reliability. If a new one is added in the middle of the project The field programmable logic array prototype hardware platform needs to redesign the comprehensive environment, with low reusability and low scalability, which cannot meet t...

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Problems solved by technology

[0002]SSD-Solid State Drives (solid state drive) SOC chip verification, due to the limitations of EDA verification, generally use FPGA propotyping verification (conditionally also use emulator( hardware acceleration emulator)), and in the current FPGA propotying verification (field programmable logic array prototype verification), there are generally multiple FPGA propotying (field programmable logic array prototype) hardware platforms, frequent iterations, traditional methods, and difficult maintenance High, low efficiency, and low reliability. If a new field programmable logic array prototype hardware platform is added in the middle of the project, it is necessary to redesign the comprehensive environment, with low reusability and low scalability, which cannot meet the needs

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