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Multiplexing LDPC encoding method

A coding method and multiplexing technology, which are applied in error detection coding, coding and coding components using multi-bit parity bits, can solve problems such as large hardware resources and non-sparse generator matrix, and achieve optimal design, It is convenient to increase or decrease and reduce the effect of resource occupancy rate

Inactive Publication Date: 2019-04-26
NO 54 INST OF CHINA ELECTRONICS SCI & TECH GRP
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Problems solved by technology

The general encoding method of LDPC code is to obtain the code word sequence by multiplying the information sequence and the generation matrix of the code. Although the parity check matrix of the LDPC code is very sparse, its generation matrix is ​​not sparse, which makes its coding complexity Often proportional to its code length, the greater the encoding complexity, the greater the number of registers required for storage during implementation, and the greater the consumption of hardware resources

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[0019] The present invention will be further described below in conjunction with specific drawings.

[0020] Usually, the timing diagram of a single-channel LDPC encoding unit is as follows figure 1 shown. It includes the text input FIFO and output FIFO, that is, IN_FIFO and OUT_FIFO in the figure, and the LDPC encoding module - ENC module. If the circuit design does not perform time-division multiplexing, the structure of encoding the multi-channel message information is as follows: figure 2 shown, that is figure 1 A multiplexed copy of the structure. The circuit structure after multiplexing is as follows image 3 As shown, multiple channels of message information share one LDPC encoding module through time-division multiplexing, which greatly simplifies the circuit design.

[0021] from figure 1 It can be seen from the timing diagram that 1PPS is a second pulse signal generated by an external time-frequency device, which is mainly used to provide a time reference for ...

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Abstract

The present invention discloses a multiplexing LDPC encoding method. The method is mainly used in an FPGA program design of an inter-station source of a satellite navigation system, and is suitable for a scenario where multi-path information all requires LDPC coding. The method performs time-division LDPC coding processing on each signal of the multi-path signals through time division multiplex, thereby realizing integration of repetitive coding modules in a hardware circuit design, optimizing the hardware circuit module design and reducing utilization of hardware resources. And the method hascharacters of novelty, creativity, simplicity practicability.

Description

technical field [0001] The invention relates to the field of LDPC coding, in particular to the multiplexing technology of LDPC coding modules in hardware circuit design. Background technique [0002] LDPC code is a linear block code with a simple representation method and easy hardware implementation. It is widely used in wireless communication, digital audio, and video broadcasting. Data transmission can be realized more securely through LDPC coding, meeting the performance requirements of high-speed data transmission in future communication systems. [0003] The LDPC module multiplexing technology is mainly used in the FPGA program design of the inter-station source of the satellite navigation system. As a kind of inter-station signal simulation source, the inter-station source needs to have multi-channel inter-station signal output capability, and each channel is independent of each other, and has the ability to output digital transmission text, that is, each channel nee...

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Application Information

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IPC IPC(8): H04L1/00H03M13/11
CPCH03M13/1148H04L1/0057H04L1/0061
Inventor 张宁韩双林闫庆霞王永杰
Owner NO 54 INST OF CHINA ELECTRONICS SCI & TECH GRP
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