3D memory device and manufacturing method thereof

Abstract

The application discloses a 3D storage device and a manufacturing method thereof. The 3D memory device includes: a semiconductor substrate; a gate stack structure located on the semiconductor substrate, including a plurality of gate conductor layers and a plurality of interlayer insulating layers stacked alternately; and a plurality of channel holes respectively arranged in In the corresponding storage area, each channel hole penetrates the stacked gate structure and is electrically connected to the semiconductor substrate; multiple isolation structures are respectively arranged in the corresponding isolation area, and each isolation structure penetrates the stacked gate structure to realize multiple Isolation between two storage areas; a plurality of conductive channels, distributed in the isolation area and the storage area, each conductive channel runs through the gate stack structure and is electrically connected to the semiconductor substrate, and each channel hole is at least connected to one conductive channel The channels are arranged adjacently, and each conductive channel is used to supply power to the channel holes around it through the semiconductor substrate. In the 3D memory device according to the embodiments of the present invention, the interlayer insulating layer will not be damaged due to excessive etching.

Description

technical field [0001] The present invention relates to memory technology, and more specifically, to a 3D memory device and a manufacturing method thereof. Background technique [0002] The improvement of the storage density of the memory device is closely related to the progress of the semiconductor manufacturing process. As the feature size of the semiconductor manufacturing process becomes smaller and smaller, the storage density of the memory device becomes higher and higher. In order to further increase storage density, memory devices with a three-dimensional structure (ie, 3D memory devices) have been developed. A 3D memory device includes a plurality of memory cells stacked in a vertical direction, which can double the integration level on a wafer per unit area and reduce the cost. [0003] Existing 3D memory devices are mainly used as non-volatile flash memory. The two main non-volatile flash memory technologies use NAND and NOR structures, respectively. Compared...

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Problems solved by technology

[0006] Secondly, in the process of forming the gate conductor layer, it is necessary to remove the sacrificial layer on both sides through the gate line spacer. Since there is a certain distance between each gate line spacer, excessive etching is required to ensure the complete removal of the sacrificial layer. , so it will damage the interlayer insulating layer close to the gate line spacer

[0007] Finally, since each conductive channel formed in the grid spacer needs to supply power to multiple rows of channel holes located on both sides of it, due to the distance between the channel holes close to the conductive channel and the channel holes far away from the conductive channel, the obtained The voltage is not uniform

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