RISC-V controller debugging method and RISC-V controller debugging device based on UART

Abstract

The invention discloses a RISC-V controller debugging method and a RISC-V controller debugging device based on a UART. The method comprise: in an FGPA, an UART debugging module is used for obtaining the operation state from a system bus; The operation state is sent to the terminal from the UART debugging module through the UART interface; At the terminal, analyzing the operation state into a working instruction, displaying the working instruction, and receiving a debugging instruction determined by a user based on the working instruction; Sending the debugging instruction from the terminal toa UART debugging module through a UART interface; In FGPA, a UART debugging module is used to debug the RISC-V controller through a system bus according to a debugging instruction. The technical scheme provided by the invention can monitor or debug aiming at different RISC-V controller chips or RISC-V controller chips in different types, so that the debugging difficulty is reduced, and the debugging speed is increased.

Description

technical field [0001] The present invention relates to the computer field, and more specifically, to a UART-based RISC-V controller debugging method and device. Background technique [0002] UART (internal integrated circuit) is widely used in the server field to control and monitor the server, the interface is simple, the operation is convenient, and it is easy to use. RISC-V (the fifth generation of reduced instruction set computer, Reduced Instruction SetComputer V) is an open instruction set architecture based on the principle of reduced instruction set computing. It has the characteristics of complete open source, simple structure, easy transplantation, and modular design. The chip based on the RISC-V instruction set was successfully taped out and the open source code based on the RISC-V instruction set. In the prior art, when the open source code of RISC-V runs on FPGA (Field Programmable Gate Array), there will be many problems, which will bring difficulties to debu...

AI Technical Summary

Problems solved by technology

In the prior art, when the open source code of RISC-V runs on FPGA (Field Programmable Gate Array), there will be many problems, which will bring difficulties to debugging, and the built-in debugging tools need specific interfaces and supporting debugging tools, and the debugging environment complex

[0003] For the problem of difficult debugging of RISC-V controller on FPGA in the prior art, there is no effective solution yet

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