Layout and wiring method suitable for improving CPU core frequency

A layout and routing, CPU core technology, applied in the field of layout and routing of CPU core frequency increase, can solve problems such as repair hold time violation, timing pessimism, impact CPU core frequency breakthrough, etc., achieve high area and controllable power consumption, simple process , The effect of speeding up the timing convergence speed

Active Publication Date: 2019-05-21
NAT UNIV OF DEFENSE TECH
View PDF2 Cites 9 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The current mainstream technology has entered the nanometer stage. Using fixed on-chip variation values ​​to constrain the timing for layout and routing will lead to overly pessimistic timing, which will affect the frequency breakthrough of the CPU core.
[0007]5. In addition to concentrating on repairing setup violation

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Layout and wiring method suitable for improving CPU core frequency

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0030] Such as figure 1 As shown, the implementation steps of the placement and routing method applicable to CPU core frequency boosting in this embodiment include:

[0031] 1) Input the design file;

[0032] 2) Set process constraints, execute layout with clock tree pre-synthesis, and do not fix hold time violations during the layout process, use useful offsets to fix setup time violations, and use advanced on-chip process changes to add different timing paths on different timing paths Process deviation value;

[0033] 3) Perform clock tree synthesis, and do not repair hold time violations during clock tree synthesis, use useful offsets to repair setup time violations, and use advanced on-chip process changes to add different process deviation values ​​to different timing paths;

[0034] 4) Execute routing to complete the routing of clock lines and signal lines according to the rules, and do not repair hold time violations during the wiring process, use useful offsets to re...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

PUM

No PUM Login to view more

Abstract

The invention discloses a layout and wiring method suitable for improving CPU core frequency. According to the invention, the physical realization layout and wiring method is improved; clock tree pre-synthesis is carried out in the layout stage; Useful offset (Useful Skew) and advanced on-chip change (AOCV) are used in the whole layout and wiring process (layout with clock tree pre-synthesis, clock tree synthesis and wiring). The whole process does not repair the retention time violation, resistance-capacitance coefficient correction is performed after wiring is completed, and then layout-clock tree synthesis-wiring with clock tree pre-integration is executed again. According to the invention, higher frequency of the CPU core can be realized, the area and the power consumption can be keptcontrollable, the time sequence convergence speed under multiple modes and multiple end angles is accelerated, and the method has the advantages of simple process, high operability and high time sequence convergence speed, and can still meet other sign-off tape-out conditions.

Description

technical field [0001] The invention relates to the technical field of integrated circuit electronic automation design of high-performance CPU cores, in particular to a layout and wiring method suitable for increasing the frequency of CPU cores. Background technique [0002] The physical implementation of high-performance CPU cores has always been a difficult point in microprocessor design, and the frequency of CPU cores directly affects the performance of microprocessors. How to increase the frequency of the CPU core from the layout and routing method of physical design is a subject worth studying. The main problems in the physical implementation of the CPU core under advanced technology are as follows: [0003] 1. As the chip technology enters the ultra-deep sub-micron stage, the influence of process parameters on device delay is becoming more and more prominent. The width of metal lines under advanced technology is reduced to only tens of nanometers, and at the same time...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

Application Information

Patent Timeline
no application Login to view more
IPC IPC(8): G06F17/50
Inventor 何小威赵振宇黄鹏程马驰远乐大珩冯超超栾晓琨贾勤
Owner NAT UNIV OF DEFENSE TECH
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Try Eureka
PatSnap group products

Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic.

© 2024 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap