An ADC with chopping stability and suitable for a sigma delta ADC structure

Abstract

The invention discloses an ADC with stable chopping and suitable for a sigma delta ADC structure, and belongs to the technical field of CMOS integrated circuit design. The circuit is composed of an input signal sampling part, a reference voltage sampling part, an integral signal establishing part, a comparator and a counter. According to the invention, a sigma delta ADC structure with stable chopping is adopted to chop the whole internal analog signal path, thereby effectively eliminating detuning and low-frequency noise, and obtaining extremely low errors and drifting. On the basis of traditional sampling, a sampling control switch for input signals is added, and on the basis of traditional biphase non-overlapping clk1 and clk2, a biphase non-overlapping clock cell _ in and a cell _ vcm are added; Wherein the periodicity of clk1 and clk2 is 2M + 1, M is the digital output digit of the ADC, and the periodicity of cell _ in and cell _ vcm is 2M. And the integration frequency of the input signal is 2M times and the integration frequency of the reference voltage is 2M + 1 times in one analog-to-digital conversion process, so that the output range of the integrator meets the requirement of the subsequent SAR ADC input range after conversion is completed, and the analog-to-digital converter is suitable for a hybrid ADC circuit.

Description

technical field [0001] The invention belongs to the technical field of CMOS integrated circuit design, and in particular relates to a chopper-stabilized ΣΔ ADC suitable for a hybrid ADC structure. Background technique [0002] With the development of semiconductor process technology and the demand of portable equipment, low voltage and low power consumption have become the main trend of integrated circuit design. As a core device that converts analog signals into digital signals, the analog-to-digital converter (ADC) is also developing in the direction of high precision, high speed, and low power consumption. For this reason, various new structure ADCs have been invented in recent years. Among them, the new hybrid structure combining Sigma-Delta (ΣΔ) ADC and successive approximation (SAR) ADC has attracted more and more attention. ΣΔADC has the advantages of simple structure, low power consumption, high precision and no need for device matching, and is widely used in commun...

AI Technical Summary

Problems solved by technology

In this structure, the traditional ΣΔ ADC cannot be used as the first stage, because in the ΣΔADC of the traditional structure, when the first stage conversion is completed, the voltage range output by the integrator is 0~Vref or -Vref~0 , and for the second-stage SAR ADC, the required input voltage range should be -Vref / 2~Vref / 2

In the patent Hybrid Delta-Sigma / SAR Analog to Digital Converter and Methods for Using Such, US2008 / 0258951A1, SAR ADC and ΣΔ common integrator and comparator are used, but this method needs to continuously change the sampling signal under the multi-phase clock , capacitance ratio, reference voltage, etc., the working clock is very complicated, and it is easy to reduce the accuracy caused by leakage

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