Minimum track standard cell circuits for reduced area

Abstract

Minimum track standard cell circuits for reduced area are provided. In one aspect, a minimum track standard cell circuit employs a first high aspect ratio voltage rail disposed over a first one-half track and configured to provide a first voltage (e.g., VDD) to the minimum track standard cell circuit. A second high aspect ratio voltage rail is disposed over a second one-half track substantially parallel to the first high aspect ratio voltage rail. The second high aspect ratio voltage rail is configured to provide a second voltage less than the first voltage (e.g., VSS) to the minimum track standard cell circuit. The minimum track standard cell circuit employs multiple tracks disposed between the first and second one-half tracks. The number of tracks can be limited based on particular factors. Minimizing tracks reduces area compared to conventional standard cell circuits.

Description

[0001] Cross References to Related Applications [0002] This application claims priority to U.S. Patent Application No. 15 / 266,523, filed September 15, 2016, entitled "MINIMUM TRACK STANDARD CANGCIRCUITS FOR REDUCED AREA," the entire contents of which are incorporated herein by reference. technical field [0003] The technology of the present disclosure relates generally to standard cell circuits, and in particular to reducing the area of ​​standard cell circuits. Background technique [0004] Processor-based computer systems may include a large number of integrated circuits (ICs). Each IC has a complex layout design consisting of multiple IC devices. Standard cell circuits are often employed to help make the design of the IC less complex and more manageable. In particular, standard cell circuits provide designers with predesigned cells corresponding to commonly used IC devices that conform to the specific design rules of the chosen technology. As non-limiting examples,...

AI Technical Summary

Problems solved by technology

[0006] However, as the technology node size shrinks to ten (10) nm and below, metal lines within conventional standard cell circuits cannot continue to scale by 30% due to gate pitch and metal pitch constraints

Therefore, conventional standard cell circuits cannot achieve the desired area reduction of about 50% at technology node sizes of 10 nm or less

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