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Address fine tuning acceleration system

An acceleration system and address technology, applied in the field of address fine-tuning acceleration system, can solve the problems of lengthening the instruction pipeline length, and achieve the effects of avoiding inconsistent errors, saving bandwidth, and reducing dynamic power consumption

Active Publication Date: 2019-05-31
HUAXIA GENERAL PROCESSOR TECH INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

But the disadvantage is that each address calculation needs to access the DTLB, which increases the pipeline length of the instruction.

Method used

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  • Address fine tuning acceleration system

Examples

Experimental program
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Effect test

Embodiment 1

[0018] Every time the address generation instruction is written back, it is checked by the way whether the address is impossible to cross pages within a certain range, and two bits are used to indicate whether it will cross two adjacent pages. The range selection can be adjusted according to the frequency of fine-tuning the immediate data, if there is no bit corresponding to the risk of page crossing. After each address fine-tuning instruction reads the base address from the register group, if the immediate value is less than the safety distance, and the address conversion of the base address register is completed, the conversion result is directly read and assigned to its own address register, and the register group is selected to read at this time. The low-order address and the immediate value are operated, and the result is written back to the low-order address register. Another optional optimization method is to separate the high bits, page attributes, and low bits of the ...

Embodiment 2

[0020] In order to meet the need to open a separate submission channel for accelerated fine-tuning instructions, the retire unit can quickly see the completion of this instruction. So far, the requirements for this type of instruction pipeline trimming have been completed. Similarly, a separate write-back channel can also be opened, and the result can be sent to the memory access module. If a separate write-back channel is opened, then this type of instruction does not need to be pushed into the reservation station, and the instruction is completed ahead of schedule at the previous level, saving The bandwidth and capacity of station transmissions are reserved. If you consider the complexity brought by the additional write-back channel to the memory access module (more logic for address dependency detection), you can push this type of acceleration instruction into the reserved station, execute normally and convert the address, and give The write-back path of the memory access m...

Embodiment 3

[0022]Open up a separate submission and write-back path, so for the sequential fine-tuning and continuous memory access sequence, the effect is that only the initial address generation instruction needs general calculation and access to DTLB once, and all subsequent memory accesses without the risk of cross-page are all unnecessary Accessing DTLB again greatly saves pipeline power consumption and achieves the ultimate power consumption ratio optimization. Pay attention to a problem here. If the compiler guarantees that every time when changing the virtual and real address mapping or page attributes, when accessing a certain address in the page that has changed the mapping, there will be an address generation instruction in advance to update the mapping and page attributes. , then no special processing is required, and the mapping information and attributes of the same page can be safely used for each address fine-tuning instruction. But if it is not guaranteed, it means that i...

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Abstract

The invention discloses an address fine tuning acceleration system in the technical field of address fine tuning. Scheduling unit, High-order physical register block, Shared mapping unit, Address checking unit, Low-order physical register block, Instant number detection unit, Real address fine tuning detection, New address generation unit, the reservation station comprises an execution and virtual-real address conversion unit and a submission unit; The output end of the scheduling unit is connected with the address checking unit through a wire. the immediate data detection unit is connected with the input end of the low-order unit; The output end of the address checking unit is connected with the reservation station through a wire. the real address fine tuning detector is connected with the input end of the low-order physical register group; According to the address fine adjustment method and device, the execution speed of the address fine adjustment instruction can be increased, the dynamic power consumption of overall address conversion is reduced, and if a certain instruction does not meet the optimization condition, the previous execution path can be kept unchanged, and performance reduction cannot occur. And one-key switching can be realized.

Description

technical field [0001] The invention relates to the technical field of address fine-tuning, in particular to an address fine-tuning acceleration system. Background technique [0002] At present, mainstream memory access instructions build address calculation information into the instruction. After the memory access module accepts the instruction, it calculates the virtual address through the internal AGU, and then inputs the virtual address into the cache and TLB at the same time to complete the access form of VIPT (virtual indexed physical tagged). Therefore, The mapping of virtual and real addresses always needs to be followed by the AGU, and address translation needs to be performed when the address is accessed. ISA determines the timing of the conversion of the virtual and real addresses of the memory access instruction. If the calculation of the memory access address is extracted separately, it becomes an independent Instructions, and define special architectural regist...

Claims

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Application Information

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IPC IPC(8): G06F12/10
CPCY02D10/00
Inventor 费晓龙王磊杨亭
Owner HUAXIA GENERAL PROCESSOR TECH INC
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