AXI2WB bus bridge implementation method, device and equipment and storage medium

Abstract

The invention discloses a method for realizing an AXI2WB bus bridge. The method comprises the following steps: latching an AXI write address channel signal and an AXI write data channel signal; Determining the number of WB transmission times required by the current AXI write data according to the multiplying power of the bit width of the AXI write data and the bit width of the WB write data; Aiming at each WB write operation, converting the AXI write address into the WB write address of the WB write operation, converting the AXI write data into the WB write data of the WB write operation, andexecuting the WB write operation based on the WB write address and the WB write data; And until the number of WB write operations reaches the number of WB transmission times required by AXI write data. By applying the technical scheme provided by the embodiment of the invention, the design of the high-speed cache-free AXI2WB bus bridge applicable to the interior of the FPGA can be realized. The invention also discloses an AXI2WB bus bridge realization device, equipment and a storage medium, which have corresponding technical effects.

Description

Technical field [0001] The present invention relates to the technical field of chip design, in particular to an AXI2WB bus bridge realization method, device, equipment and storage medium. Background technique [0002] At present, SoC (System on Chip, System on Chip) has become a mainstream technology for large-scale digital integrated circuit design. SoC chips are generally composed of multiple IP modules, such as embedded CPUs, DSPs, various functional modules, storage modules, and external interface modules. The master module and the slave module are connected by an on-chip bus to complete the transmission of control signals and data signals. The most widely used SoC bus protocol is ARM's AMBA (Advanced Microcontroller Bus Architecture) bus protocol. The AMBA bus protocol includes AXI (Advanced eXtensible Interface, advanced extensible interface), AHB (Advanced High-performance Bus, Advanced high-performance bus), APB (Advanced Peripheral Bus, Advanced Peripheral Bus) and oth...

AI Technical Summary

Problems solved by technology

When the peripherals are directly mounted on the AXI bus, the peripheral interface needs to be encapsulated into the AXI protocol. Due to the large number of AXI bus protocol signals, when the number of peripherals is large, the interface of each peripheral needs to be encapsulated into an AXI interface, resulting in work Large volume, low work efficiency

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