A delay locked loop and a delay locked method

Abstract

The invention provides a delay locking ring and a delay locking method. The delay locking ring comprises the following steps: delaying an analog main delay line of a reference clock signal based on amain delay control word; enabling the digital phase discrimination module identify the phase difference before and after the reference clock signal delay; the digital main control module is used for adjusting the main delay control word based on the phase difference and assigning the main delay control word corresponding to the delay period to the set delay control word; the digital slave controlmodule takes a set delay control word with a set proportion as a slave delay control word; an analog slave delay line that delays an input clock signal is controlled based on the slave delay control word. Controlling the reference clock signal to be delayed for a period based on the phase-locked loop; assigning the corresponding main delay control word to a set delay control word, multiplying themain delay control word by a set proportion, and adjusting the delay of the input clock signal. According to the invention, the digital phase discriminator and the digital controller are adopted, thereliability is high, and a loop is more stable; and an analog delay line is adopted, so that delay adjustability can be realized, and the circuit debugging difficulty is reduced.

Description

technical field [0001] The invention relates to the field of integrated circuits, in particular to a delay-locked loop and a delay-locked method. Background technique [0002] With the development of modern integrated circuit technology, the scale of the chip continues to increase, and the operating frequency continues to increase. The quality of on-chip clock distribution and clock delay become more and more important. The Delay Locked Loop (DLL) can meet the precise synchronization requirements of the on-chip high-speed clock, eliminate clock delay, realize zero transmission delay, and minimize the deviation between the clock input signal and the internal clock pin of the entire chip. As a very important part of integrated circuit design, delay locked loops have gradually become the focus of attention, and are widely used in various SoC (System on Chip, System on Chip) chips. [0003] In the application of the SDIO (Secure Digital Input and Output, secure digital input an...

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Problems solved by technology

[0005] In view of the above-mentioned shortcomings of the prior art, the object of the present invention is to provide a delay-locked loop and a delay-locked method, which are used to solve the problems of complex timing and poor accuracy of the delay-locked loop in the prior art.

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