Bonding structures and methods of forming them

Abstract

The present invention relates to a bonding structure and a forming method thereof. The forming method of the bonding structure includes: providing a first substrate, an electrical contact part is formed in the first substrate, and the first substrate has an opposite first substrate. surface and a second surface, the surface of the electrical contact portion is flush with the first surface of the first substrate; a second substrate is provided, and a bonding medium layer is formed on one side surface of the second substrate; The second substrate is bonded to the first surface of the first substrate through the bonding medium layer; a semiconductor device is formed on the other surface of the second substrate. The bonding quality of the bonded structure is improved.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a bonding structure and a forming method thereof. Background technique [0002] In recent years, the development of flash memory (Flash Memory) is particularly rapid. The main feature of flash memory is that it can keep stored information for a long time without power on, and has the advantages of high integration, fast access speed, easy erasing and rewriting, etc. Has been widely used. In order to further increase the bit density (Bit Density) of the flash memory while reducing the bit cost (Bit Cost), three-dimensional flash memory (3D NAND) technology has been developed rapidly. [0003] In the 3D NAND flash memory structure, it includes a storage array structure and a CMOS circuit structure located above the storage array structure. The storage array junction and the CMOS circuit structure are usually formed on two different wafers respectively, and then by hybrid b...

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Problems solved by technology

[0004] The hybrid bonding method requires strict alignment of the two wafers. Once there is a misalignment, the connection will fail and the yield will decrease.

Moreover, since the memory array wafer has a complex thin-film stack structure

During the bonding process of CMOS circuit wafers and storage array wafers, problems such as bubbles, peeling and even fragments are prone to occur. There are extremely high requirements for the quality of the contact interface of the wafers. The difference in deformation and stress between the two sides can easily lead to misalignment problems.

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