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A Method for Automatic Delay Matching of Asynchronous Circuit

An asynchronous circuit and delay matching technology, which is applied in CAD circuit design and other directions, can solve problems such as difficulty in delay matching and failure to capture timing paths, and achieve the effect of reducing difficulty and design difficulty

Active Publication Date: 2021-06-08
TSINGHUA UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Since there is no clock, DC tools cannot capture the timing paths in bundled data asynchronous circuits, which makes delay matching difficult

Method used

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  • A Method for Automatic Delay Matching of Asynchronous Circuit
  • A Method for Automatic Delay Matching of Asynchronous Circuit
  • A Method for Automatic Delay Matching of Asynchronous Circuit

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Embodiment Construction

[0026] The implementation of the present invention will be described in detail below in conjunction with the drawings and examples.

[0027] The structure of the Click unit is as follows figure 1 As shown, its waveform is shown in figure 2 shown. From figure 1 and figure 2 It can be seen that the Click unit uses a two-phase handshake protocol, that is, each flip of the request signal represents a request. Each time a request is requested, the Click unit will generate a fire pulse signal. This fire pulse signal can actually be regarded as a clock to capture and store data.

[0028] Use the Click unit to design a bundled data asynchronous circuit. The structure of the circuit is as follows image 3 As shown, "bundled data" means that the data signal adopts a Boolean value, and the request (request) and acknowledge (acknowledge) lines are separated from each other and bundled together with the data.

[0029] exist image 3 In the circuit shown, i_r1 is used as the input...

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Abstract

The invention can realize automatic delay matching for the asynchronous circuit of bundled data based on the Click unit, so that it can work normally. Asynchronous circuits that bundle data require delay matching to make the circuit work properly, but designers cannot directly use mature commercial EDA tools to do this job. In order to solve this problem, the present invention provides a method capable of capturing all timing paths based on the Synopsys Design Compiler (DC) tool and automatically performing delay matching on the bundled data asynchronous circuit based on the Click unit. The invention can automatically perform delay matching for the bundled data asynchronous circuit so that the asynchronous circuit can work normally, and greatly reduces the design difficulty of the asynchronous circuit.

Description

technical field [0001] The invention belongs to the technical field of integrated circuit design, in particular to a method for automatic delay matching of an asynchronous circuit. Background technique [0002] With the continuous improvement of integrated circuit manufacturing technology, asynchronous circuits have the advantages of low power consumption, high speed and no clock distribution problems compared with synchronous circuits. However, there are many types of asynchronous circuits, and different types of asynchronous circuits have different design methods, and mature EDA tools only support synchronous circuit design, which brings difficulties to asynchronous circuit design. The asynchronous circuit based on the bundled data of the Click unit is most similar to the synchronous circuit, so it can be designed with the help of mature EDA tools. The design of bundled data asynchronous circuit requires delay matching to make the circuit meet the timing constraints and m...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F30/35
Inventor 陈虹吴辉
Owner TSINGHUA UNIV
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