Memory erasing method and device
A memory and over-erase technology, used in static memory, read-only memory, information storage, etc., can solve the problem of low programming operation efficiency, and achieve the effect of improving programming efficiency, increasing threshold voltage, and speeding up programming.
Pending Publication Date: 2019-06-11
GIGADEVICE SEMICON (BEIJING) INC
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Problems solved by technology
[0005] The present invention provides a memory erasing method and device to solve the existing problems of leakage current during read operation and low programming operation efficiency in the existing memory over-erasing verification process
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[0022] The present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the present invention, but not to limit the present invention. In addition, it should be noted that, for the convenience of description, only some structures related to the present invention are shown in the drawings but not all structures.
[0023] In addition, it should be noted that, for the convenience of description, only parts related to the present invention are shown in the drawings but not all content. Before discussing the exemplary embodiments in more detail, it should be mentioned that some exemplary embodiments are described as processes or methods depicted as flowcharts. Although the flowcharts describe various operations (or steps) as sequential processing, many of the operations may be performed in parallel, concurrently, or simultaneou...
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The embodiment of the invention discloses a memory erasing method and device. The memory erasing method comprises the following steps: carrying out erasing operation on memory cells arranged in an erasing area; when a read verification operation in the first over-erase verification operation is performed on the storage unit, sequentially selecting the storage unit, applying a first voltage to a word line connected with the selected storage unit, and applying a zero voltage to an unselected word line to obtain a storage unit of which the threshold voltage is smaller than a first set threshold;when programming operation in the first over-erase verification operation is carried out on the storage unit, the storage units with the threshold voltages smaller than a first set threshold value aresequentially selected, second voltage is applied to the word lines connected with the storage units with the selected threshold voltages smaller than the first set threshold value, and zero voltage isapplied to the unselected word lines. According to the technical scheme provided by the embodiment of the invention, the problems of current leakage and low programming operation efficiency during reading operation in an existing memory over-erasing verification process can be solved.
Description
technical field [0001] Embodiments of the present invention relate to the technical field of semiconductor storage, and in particular, to a memory erasing method and device. Background technique [0002] When performing an erase (ERASE) operation on a non-volatile memory (for example, NOR-FALSH), the final threshold voltage (Threshold Voltage) of different memory cells will be different, and some memory cells will be over-erased, and also That is, the threshold voltage is lower. In other operations, such as read operation and verify operation, the gate voltage of unselected devices is 0, and there is still leakage current (Leakage Current) for over-erased devices, so that the actual and sense amplifier (Sense Amplifier) The current to be measured compared with the reference current will become larger. When the over-erasing effect is significant or the memory array is large and there are many unselected cells, this situation will be more prominent, and the possibility of dat...
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Login to View More IPC IPC(8): G11C16/14G11C16/34
Inventor 张建军芮亚明马向超
Owner GIGADEVICE SEMICON (BEIJING) INC