Method of forming three-dimensional memory and three-dimensional memory

Abstract

The present invention relates to a method of forming a three-dimensional memory and a three-dimensional memory. The method includes the steps of: providing a semiconductor structure having a substratelocated on a back side of the semiconductor structure and a first stack located on the substrate, wherein the first stack located on a front side of the semiconductor structure; forming a plurality of first channel holes passing through the first stack from the front side; putting a sacrificial layer in the first channel hole; overturning the semiconductor structure and thinning the substrate; forming a second stack stacked on the first stack from a back side; forming a plurality of second channel holes passing through the second stack and reaching the sacrificial layer; removing the sacrificial layer; and forming a plurality of vertical channel structures in the plurality of first channel holes and the plurality of second channel holes.

Description

technical field [0001] The present invention mainly relates to a semiconductor manufacturing method, and in particular to a method for forming a three-dimensional memory and a three-dimensional memory. Background technique [0002] In order to overcome the limitations of two-dimensional memory devices, memory devices with a three-dimensional (3D) structure have been developed and mass-produced in the industry, which improves integration density by three-dimensionally arranging memory cells on a substrate. [0003] In a three-dimensional memory device such as 3D NAND flash memory, a memory array may include a core region having a channel structure. The channel structure is formed in the channel hole vertically penetrating through the stack of the three-dimensional memory device. The channel holes of the stacked layers are usually formed by a single etch. However, in order to increase the storage density and capacity, the number of layers (tier) of the three-dimensional memo...

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Problems solved by technology

For example, deposition-etch-deposition steps are required to achieve good filling, especially without pitting in the top few layers, these steps lead to higher process costs, and excessive sacrificial layer filling can cause wafer warpage

As another example, the sacrificial layer may remain, or the removal of the sacrificial layer may cause damage to the silicon epitaxial layer, resulting in the failure of the memory cell

For another example, when the alignment of the upper and lower channel holes is poor, the plasma used for etching will also damage the stacked layers of the stack, and it is easy to cause premature sealing during the process of filling the channel structure, especially in the upper and lower stacked layers. joint position

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