Compiling method based on OPU instruction set and compiler

Abstract

The invention discloses a compiling method based on an OPU instruction set and a compiler, and relates to the field of compiling methods based on CNN acceleration. The method comprises the following steps: converting CNN definition files of different target networks, selecting an optimal accelerator to configure mapping according to defined OPU instruction sets, and generating instructions of different target networks to complete mapping; wherein the conversion comprises file conversion, layer recombination of a network and generation of a unified intermediate representation IR; wherein the mapping comprises the steps of analyzing the IR, searching a solution space according to the analysis information to obtain a mapping mode for ensuring the maximum throughput, and generating instructions of different target networks based on the solved mapping mode according to the defined OPU instruction set. According to the method, the communication delay problem of an off-chip memory and the optimal accelerator configuration problem of finding different target networks are overcome, instructions of different target networks which can be executed by an OPU are output, CNN acceleration is completed by means of instruction configuration, and an FPGA accelerator is not reconstructed.

Description

technical field [0001] The invention relates to the field of CNN-accelerated compilation methods, in particular to a compilation method and a compiler based on an OPU instruction set. Background technique [0002] Deep convolutional neural networks (CNNs) have demonstrated high accuracy in various applications, such as visual object recognition, speech recognition, and object detection, etc. However, its breakthrough in accuracy comes at the cost of high computational cost, which needs to be accelerated by computing clusters, GPUs and FPGAs. Among them, the FPGA accelerator has the advantages of high energy efficiency, good flexibility, and strong computing power, especially in deep CNN applications on edge devices such as speech recognition and visual object recognition on smartphones; it usually involves architecture exploration and optimization , RTL programming, hardware implementation and software-hardware interface development. With the development, people have conduc...

AI Technical Summary

Problems solved by technology

But existing FPGA acceleration work aims to generate specific separate accelerators for different CNNs, which guarantees reasonable high performance for RTL-based or HLS-RTL-based templates, but with high hardware upgrade complexity in case of tuning the target network

Therefore, in order to realize that there is no need to generate specific hardware description code for a separate network, and it does not involve reprogramming the FPGA, the entire deployment process is completed by command configuration. Different target network configurations are configured through commands, and the FPGA accelerator is not reconfigured. An instruction set needs to be defined. , the compiler compiles the defined instruction set to generate instruction sequences, but in the compilation process, it faces the problem of off-chip memory communication delay and different target networks How to solve the universality problem of optimal performance configuration

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