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Thin film transistor and array substrate

A technology of thin film transistors and array substrates, applied in the display field, can solve the problems of reducing the transmittance of a single board, and achieve the effect of improving the transmittance of a single board and reducing the impact.

Inactive Publication Date: 2019-08-09
SHENZHEN CHINA STAR OPTOELECTRONICS TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] However, due to the arrangement of the silicon nitride layer 131, the single-plate transmittance of the array substrate 100 is reduced.

Method used

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  • Thin film transistor and array substrate
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  • Thin film transistor and array substrate

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0031] Example 1. Thin Film Transistor

[0032] In this embodiment, a thin film transistor 1 is provided, such as figure 2 As shown, the thin film transistor 1 is formed on a film-forming substrate 10, and includes: a gate 12 disposed on the film-forming substrate 10, a gate insulating layer 14 covering the gate 12, and disposed on the film-forming substrate 10. The semiconductor active layer 16 on the gate insulating layer 14 , and the source electrode 181 and the drain electrode 183 disposed on the semiconductor active layer 16 . The material of the semiconductor active layer 16 is indium gallium zinc oxide (IGZO).

[0033] Such as figure 2 As shown, the gate insulating layer 14 includes: a first gate insulating layer 141 covering the gate 12 , and a second gate insulating layer 143 disposed on the first gate insulating layer 141 . The thickness of the gate insulating layer 14 is less than or equal to 700 nm, and the thickness of the first gate insulating layer 141 is 8...

Embodiment 2

[0040] Example 2. Thin Film Transistor

[0041] In this embodiment, a thin film transistor 2 is provided, such as Figure 3A and Figure 3B As shown, the thin film transistor 2 is formed on a film-forming substrate 20, and includes: a gate 22 disposed on the film-forming substrate 20, a gate insulating layer 24 covering the gate 22, and disposed on the film-forming substrate 20. The semiconductor active layer 26 on the gate insulating layer 24 , and the source electrode 281 and the drain electrode 283 disposed on the semiconductor active layer 26 .

[0042] Different from the thin film transistor 1 in Embodiment 1, the gate insulating layer 24 of the thin film transistor 2 in this embodiment includes a first gate insulating layer 241, a second gate insulating layer 243 and a third gate insulating layer 245 . In this embodiment, the third gate insulating layer 245 may be as Figure 3A The shown arrangement is between the first gate insulating layer 241 and the second gate i...

Embodiment 3

[0046] Example 3. Array substrate

[0047] In this embodiment, an array substrate 3 is provided, and the array substrate 3 includes a plurality of thin film transistors arranged in an array. Figure 4 Described is the thin film transistor structure in a pixel unit on the array substrate 3 . As an example, Figure 4 The array substrate 3 shown in the figure includes: a base substrate 30, a thin film transistor 1 disposed on the base substrate 30, a first passivation layer 32 covering the thin film transistor 1, disposed on the first A color resist layer 34 on a passivation layer, a second passivation layer 36 disposed on the color resist layer 34 , and a pixel electrode 38 disposed on the second passivation layer 36 . Such as Figure 4 As shown, the pixel electrode 38 is connected to the drain electrode 183 of the thin film transistor 1 through the first passivation layer 32 and the second passivation layer 36 .

[0048] Those skilled in the art can understand that the arra...

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Abstract

The invention provides a thin film transistor and an array substrate using the same. A first gate insulating layer with the refractive index of 1.45 to 1.75 is added into a gate insulating layer. A gate can be protected, and the influence on the transmittance of a veneer is reduced.

Description

technical field [0001] The invention relates to the field of display technology, in particular to a thin film transistor, an array substrate and a display panel. Background technique [0002] With the development of high-resolution display technology, in recent years, a scheme of using indium gallium zinc oxide (InGaZnOx, IGZO) instead of a silicon semiconductor film to form a channel layer of a thin film transistor has been proposed, which is called IGZO-TFT technology. Since IGZO has a higher mobility than amorphous silicon and can be formed through a simpler process, it has been used more and more. [0003] See figure 1 , figure 1 It is a structural schematic diagram of an array substrate of an existing IGZO-TFT technology. Such as figure 1 As shown, the array substrate 100 includes: a base substrate 110, a gate 120 disposed on the base substrate 110, a gate insulating layer 130 covering the gate 120, disposed on the gate insulating The IGZO film layer 140 on the lay...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L29/423H01L29/49H01L29/51H01L29/786H01L27/12
CPCH01L27/1214H01L29/42364H01L29/42384H01L29/4908H01L29/513H01L29/7869
Inventor 陈黎暄
Owner SHENZHEN CHINA STAR OPTOELECTRONICS TECH CO LTD
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