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Preparation method of shallow trench isolation structure

An isolation structure and shallow trench technology, which is applied in the field of preparation of shallow trench isolation structures and can solve problems such as damage to isolation trenches

Active Publication Date: 2021-10-15
CSMC TECH FAB2 CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0006] Based on this, it is necessary to provide a method for preparing a shallow trench isolation structure for the plasma generated during the deposition process to damage the surface oxide layer of the isolation trench, thereby causing leakage.

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  • Preparation method of shallow trench isolation structure
  • Preparation method of shallow trench isolation structure
  • Preparation method of shallow trench isolation structure

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Embodiment Construction

[0040] In order to make the above objects, features and advantages of the present invention more comprehensible, specific implementations of the present invention will be described in detail below in conjunction with the accompanying drawings. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, the present invention can be implemented in many other ways different from those described here, and those skilled in the art can make similar improvements without departing from the connotation of the present invention, so the present invention is not limited by the specific embodiments disclosed below.

[0041] See figure 1 , an embodiment of the present application provides a method for preparing a shallow trench isolation structure, comprising the following steps:

[0042] S100: Provide a semiconductor substrate.

[0043] Semiconductor substrates are semiconductor materials that provi...

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Abstract

The invention relates to a method for preparing a shallow trench isolation structure, comprising: providing a semiconductor substrate; forming a second dielectric layer on the semiconductor substrate; etching the second dielectric layer and the semiconductor substrate, to Forming isolation grooves; forming a third dielectric layer at the bottom and side walls of the isolation grooves; forming a fourth dielectric layer on the surface of the second dielectric layer and the surface of the third dielectric layer; depositing an insulating medium in the isolation grooves , to form a shallow trench isolation structure. In the manufacturing process of the above shallow trench isolation structure, after the third dielectric layer is grown on the bottom and sidewalls of the isolation trench, a relatively dense fourth dielectric layer is grown on the surfaces of the third dielectric layer and the second dielectric layer. The fourth dielectric layer can effectively block the damage to the surface of the third dielectric layer by the plasma generated when depositing the insulating medium in the isolation groove, and play a blocking role, thereby preventing electric leakage from being caused.

Description

technical field [0001] The invention relates to the field of semiconductors, in particular to a preparation method of a shallow trench isolation structure. Background technique [0002] With the development of integrated circuits, the manufacture of integrated circuits has entered the deep submicron era, and the traditional intrinsic oxidation isolation technology has been replaced by shallow trench isolation technology. [0003] Shallow Trench Isolation (STI) technology is a process for fabricating isolation regions between active regions of transistors on a substrate, which can effectively ensure that N-type and P-type doped regions are completely isolated. Usually, the silicon wafer is first thermally oxidized to form a buffer layer, and then a silicon nitride layer is deposited, and isolation grooves are dug out by photolithography and etching, and the surface of the isolation grooves is oxidized. Oxide is then deposited by chemical vapor deposition and planarized. The...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/762H01L21/02
CPCH01L21/0217H01L21/76224
Inventor 孙晓峰秦仁刚盛拓
Owner CSMC TECH FAB2 CO LTD