Function verification structure for artificial intelligence processor chip

Abstract

The invention discloses a function verification structure for an artificial intelligence processor chip. The function verification structure comprises a vector listener, a domain duplex transceiver, avector comparator and an interface formatting mode. The interface formatting mode automatically generates a vector packet and a vector listener after the interface formatting mode is processed by a scripting language, and automatically integrates the vector listener into a function verification structure. The vector listener collects an input / output interface vector packet of the artificial intelligence processor function module. The domain duplex transceiver sends an input interface vector packet of the processor function module to an artificial intelligence software model control domain, and returns a processing result to the vector comparator. The vector comparator compares and judges an output vector packet of the processor function module and an output vector packet processed by theartificial intelligence software model control domain. According to the structure, the complexity of collaborative development of artificial intelligence software and hardware is reduced, the development efficiency of the artificial intelligence processor chip is improved, and the convergence period and the chip research and development period of function verification of the artificial intelligence processor chip are remarkably shortened.

Description

technical field [0001] The invention belongs to the field of artificial intelligence, and in particular relates to a function verification structure for an artificial intelligence processor chip. Background technique [0002] Chip functional verification means that the verification team builds a suitable verification platform based on the functional design description of the chip, finds out the lack of functions and performance defects before chip production, and assists the chip design team to test its repair plan. High-quality and efficient functional verification is an important guarantee to ensure that chips are produced on time and with high quality. [0003] Artificial intelligence processor chips need to process massive amounts of vector data, need to support continuously developing deep learning networks such as Vggnet, Resnet, and Yolo, and need to be developed collaboratively with artificial intelligence software, all of which pose higher challenges to the chip fun...

AI Technical Summary

Problems solved by technology

[0004]The current mainstream chip function verification structure such as the UVM unified verification methodology platform is based on the System Verilog (SV) language, which was produced before the rise of artificial intelligence chips, focusing on Fine-grained control at the physical level of the chip, less consideration of support for vectors and tensors, and lack of interconnection with artificial intelligence software models

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