A high-speed comparator and its analog-to-digital converter and readout circuit

Abstract

A high-speed comparator disclosed by the present invention includes a first MOS transistor, a second MOS transistor, a third MOS transistor, a fourth MOS transistor, a fifth MOS transistor, a sixth MOS transistor, a seventh MOS transistor, and a clamping MOS transistor , the first capacitor, the second capacitor and the third capacitor; the present invention adds a clamp MOS tube between the A node and the B node, so that when the output signal of the comparator jumps, the voltage difference between A and B will not exceed The gate-source turn-on voltage drop of the MOS transistor is clamped, so that the drain end of the first MOS transistor connected to the ramp signal does not experience a large jump, thereby achieving the effect of stabilizing the ramp signal.

Description

technical field [0001] The invention relates to the field of integrated circuits, in particular to a high-speed comparator and its formed analog-to-digital converter and readout circuit. Background technique [0002] CMOS image sensors have been widely used in imaging fields such as video, surveillance, industrial manufacturing, automobiles, and home appliances. The readout circuit of the CMOS image sensor is based on the column-level single-slope analog-to-digital converter (SS-ADC). The function of the SS-ADC is to compare the signal to be quantized with a ramp reference signal. The result is finally quantized by a counter to obtain an N-bit binary digital quantity. One of the most core circuits in SS-ADC is the comparator. The function of the comparator is to judge the magnitude of the ramp signal voltage and the signal voltage to be quantized, and output a "1" or "0" signal as the basis for subsequent counter quantization. . [0003] When the image sensor output circu...

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Problems solved by technology

[0003] When the image sensor output circuit is working, the output signal of the comparator will jump from high to low. Due to the large gain of the comparator, the jump range is relatively large, and the signal jump will be fed back through the parasitic capacitance of the comparator. To the input terminal of the comparator, resulting in high-to-low jitter of the ramp signal, which makes the ramp signal deviate, and eventually causes the output of the other column comparators to shift, resulting in an error in the output of its single-slope analog-to-digital converter

For example, when the signal potentials of some columns are high, the comparators of these columns flip first, and the ramp signal deviates, so that when the comparators of some columns with low signal potentials flip later, because the ramp has already occurred If there is a deviation, the output result of the comparator will also deviate, and the conversion results of the converted columns of the ADC will be wrong.

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