A high-speed low-power comparator, successive approximation analog-to-digital converter, and electronic equipment

Abstract

The invention discloses a high-speed and low-power comparator, which includes an input NMOS transistor M1 / M2, a latch structure composed of an NMOS transistor M4 / M5 and a PMOS transistor M7 / M8, and a latch structure composed of an NMOS transistor M6 and a PMOS transistor M9. The reset control switch is a pull-down tube composed of NMOS tubes M3 / M10 / M11; it also includes inverters I0 / I1 / I2, delay units d1 / d2, AND gates AND1 / AND2, and same-OR gates XNOR; the present invention adopts Add a NOR gate to the pull-down tube for control to prevent static power consumption caused by the conduction of the channel where tip and tin are located and the pull-down tube, and add two reset switches so that the output Dp and Dn will not be pulled down to 0 or pulled up to Vdd, and then the comparator quickly enters the latch, so as to achieve the effect of small voltage change, less capacitance repetition, and low power consumption. In addition, the noise can be suppressed by the existing successive approximation analog-to-digital converter and the comparator. In electronic equipment, it realizes a wide range of application values.

Description

technical field [0001] The invention relates to the technical field of analog or digital-analog hybrid integrated circuits, in particular to a high-speed, low-power noise suppression dynamic comparator. Background technique [0002] In recent years, there has been increasing research on the successive approximation analog-to-digital converter (SARADC), which can provide very low power consumption and consume a small area because no operational amplifier is required. Because SARADC needs to provide fast working speed and small internal power consumption, the design of dynamic comparator becomes an important bottleneck technology of SARADC. With the continuous development of integrated circuit manufacturing technology, the feature size of CMOS devices is continuously reduced, and the operating voltage of integrated circuits is also continuously reduced. Under the deep submicron technology, the working speed of analog-to-digital converters has been greatly improved. , the powe...

AI Technical Summary

Problems solved by technology

[0006] In view of the above-mentioned shortcoming of the prior art, the purpose of the present invention is to provide a high-speed low-power comparator and successive approximation analog-to-digital converter and electronic equipment, for solving the existing dynamic comparator power consumption and speed can not be compatible problems, especially to solve the problem of dynamic comparator power consumption

Images