Radiation-tolerant metal-oxide semiconductor field effect transistor
A technology of oxide semiconductors and field effect transistors, applied in the field of radiation-resistant metal oxide semiconductor field effect transistors, to achieve the effect of reducing the impact
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Embodiment 1
[0123] Figure 8 It is a diagram of the layout of a radiation-resistant metal-oxide-semiconductor field-effect transistor resistant to single event effect and total dose effect corresponding to Embodiment 1 of the present invention.
[0124] refer to Figure 8 , In Embodiment 1, three types of dummy drain, deep N well layer and N well layer are applied. In this case, if Figure 16 It is shown in purple (Drain Current (DGA NMOS with DD, NW, and DNW)), and it can be seen that the current pulse based on the single event effect is the smallest.
Embodiment 2
[0126] Figure 9 It is a diagram of the layout of a radiation-resistant metal-oxide-semiconductor field-effect transistor resistant to single event effect and total dose effect corresponding to Embodiment 2 of the present invention.
[0127] and, Figure 10a Shows Figure 9 XX’ section of the layout, Figure 10b Shows Figure 9 The YY' section of the layout.
[0128] refer to Figure 9 , Embodiment 2 is the case of using the N- active layer and the N+ layer, and the N+ / metal-1 through hole part is only applicable to the dummy drain. Compared with Embodiment 1, this layout can be realized with a relatively narrow area, and it can be used when, for example, Embodiment 1 violates a specific design rule of a commercial process or cannot use a deep N-well layer. In the case of Example 2, as in Figure 16 It is shown in cyan (Drain Current (DGA NMOS with Dummy Drain (DD))) in the middle, and it can be seen that the current pulse due to the influence of the single event effect...
Embodiment 3
[0130] Figure 11 It is a diagram of the layout of a radiation-resistant metal-oxide-semiconductor field-effect transistor resistant to single event effect and total dose effect corresponding to Embodiment 3 of the present invention.
[0131] and, Figure 12a Shows Figure 11 XX’ section of the layout, Figure 12b Shows Figure 11 The YY' section of the layout.
[0132] refer to Figure 11 , Embodiment 3 is the case where only the deep N well layer is applied to the dummy drain and the bottom surface.
[0133] More specifically, the N-well (N-well; NW) is not in the form surrounding the radiation-tolerant MOSFET of the embodiment of the present invention, but has a form in which a deep N-well layer is arranged on the bottom surface. formed on the basis of Figure 11 The PN junction between the substrate of the structure shown and Deep N-well (DNW) cannot apply additional voltage to the bottom surface, so the current pulse caused by the single event effect does not flow ...
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