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Three-dimensional barrier-limited silicon-based impurity atomic transistor and preparation method thereof

A technology of impurity atoms and transistors, which is applied in the fields of semiconductor devices, semiconductor/solid-state device manufacturing, electrical components, etc., to achieve the effect of optimizing the preparation process, the preparation method is simple, and the limitation of the three-dimensional barrier is strengthened.

Active Publication Date: 2019-10-01
INST OF SEMICONDUCTORS - CHINESE ACAD OF SCI
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  • Three-dimensional barrier-limited silicon-based impurity atomic transistor and preparation method thereof
  • Three-dimensional barrier-limited silicon-based impurity atomic transistor and preparation method thereof
  • Three-dimensional barrier-limited silicon-based impurity atomic transistor and preparation method thereof

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Embodiment Construction

[0045] In order to make the objectives, technical solutions, and advantages of the present invention clearer, the following further describes the present invention in detail with reference to specific embodiments and drawings.

[0046] The present invention is based on a junctionless silicon nanowire transistor, and proposes a silicon-based impurity atom transistor restricted by a three-dimensional barrier. The invention uses gate-controlled impurity quantum dot energy levels and confinement barriers to realize electron tunneling through quantum dots. . The U-shaped double-barrier electrode structure modulates the impurity atom bound barrier between the two bars, while the single-barrier electrode structure modulates the energy level depth of the impurity atom to achieve a deep energy barrier bound impurity atom, thereby increasing impurities Working temperature of atomic quantum dots.

[0047] In order to solve the above technical problems, the present invention provides a silico...

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Abstract

A three-dimensional barrier-limited silicon-based impurity atomic transistor and a preparation method thereof are provided. The impurity atomic transistor at least comprises a source silicon conductive mesa and a drain silicon conductive mesa symmetrically distributed on an SOI substrate, a silicon nanowire structure located on the SOI substrate and connecting the source silicon conductive mesa and the drain silicon conductive mesa, a thin oxide layer prepared on the surfaces of the source silicon conductive mesa, the drain silicon conductive mesa and the silicon nanowire structure, a U-shapeddouble-grid electrode structure covering the thin oxide layer of the silicon nanowire structure and perpendicular to the silicon nanowire structure, and a single-grid electrode structure covering thethin oxide layer of the silicon nanowire structure, perpendicular to the direction of silicon nanowires and located in the middle of the two grids of the U-shaped double-grid electrode structure. Through the U-shaped double-grid electrode structure of the three-dimensional barrier-limited silicon-based impurity atomic transistor provided by the invention, the three-dimensional barrier restrictionof impurity atomic quantum dots is enhanced, and the working temperature is improved.

Description

Technical field [0001] The invention relates to the field of nanostructure transistors and their preparation, in particular to a silicon-based impurity atom transistor restricted by a three-dimensional barrier and a preparation method thereof. Background technique [0002] Junction-free silicon nanowire transistors are an important research direction for sub-10nm devices. Since the ionized impurity atoms are subject to dielectric and space constraints in such a small channel space, they can work as quantum dots. The gate voltage can modulate the energy level of the impurity atom quantum dot and its binding potential, and control the tunneling of electrons to transport through the ionized impurity atom. This also makes transistors that impurity atoms work as quantum dots become a research hotspot. [0003] The main mechanism of gate modulation of impurity atom quantum dots is to modulate the ground state energy level and barrier height of quantum dots covering the channel region t...

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L29/06H01L21/336H01L29/78
CPCH01L29/0669H01L29/66477H01L29/78
Inventor 张晓迪韩伟华
Owner INST OF SEMICONDUCTORS - CHINESE ACAD OF SCI
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