Packaging structure and forming method thereof

Abstract

The invention relates to a packaging structure and a forming method thereof. The forming method comprises the steps of: providing a plurality of semiconductor chips, wherein the functional surface ofeach semiconductor chip is provided with a bonding pad and a metal bump, the functional surface is also provided with a first plastic packaging layer, and the first plastic packaging layers cover themetal bumps; providing a carrier plate; forming a plurality of wiring layers on the surface of the carrier plate, and forming connecting pieces on the wiring layers; adhering the non-functional surfaces of the plurality of semiconductor chips to the carrier plate on one side of the connecting pieces; forming second plastic packaging layers coating the side walls of the semiconductor chips and thefirst plastic packaging layers on the non-functional surfaces on the carrier plate; performing planarizing to remove part of the first plastic packaging layers and the second plastic packaging layerson the carrier plate, and exposing the top surfaces of the metal bumps; and forming external contact structures connected with the metal bumps on the surfaces of the planarized first plastic packaginglayers and the planarized second plastic packaging layers. According to the method, the electrical connection performance of the rewiring layer and the bonding pad in the packaging structure is improved.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a fan-out packaging structure and a forming method thereof. Background technique [0002] Chip fan-in packaging is a manufacturing method in which rewiring and solder ball bumps are prepared on the entire wafer, and finally cut into individual chips. The final package size of this kind of package is equivalent to the chip size, which can realize the miniaturization and light weight of the package, and has a wide range of applications in portable devices. Although chip fan-in packaging can greatly reduce the packaged chip size, the number of balls on a single chip is limited, and this wafer packaging form is difficult to apply to chips with high-density I / O ports. Therefore, for chips with relatively high I / O density, if wafer-level packaging is performed, in order to ensure that the chip to be packaged and the printed circuit board can form an interconnection, the high...

AI Technical Summary

Problems solved by technology

[0004] However, in the packaging structure formed by the existing chip fan-out packaging process, the electrical connection between the wiring layer and the semiconductor chip is easily unstable, which affects the performance of the packaging structure.

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