Clock regeneration delay chain with high precision and low kickback noise

A delay chain, high-precision technology, used in clocks, time-to-digital converters, devices for measuring time intervals, etc. Phase interval consistency, guaranteed duty cycle consistency, and improved anti-noise performance

Active Publication Date: 2020-01-10
XIDIAN UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] However, the traditional voltage-controlled delay unit does not have anti-interference ability and clock regeneration ability, the phase interval of the output multi-phase clock is inconsistent, the duty cycle consistency is poor, the phase noise is high, the phase separation accuracy is low, and the voltage discrimination of similar delay times is low. , highly susceptible to environmental noise, unable to adapt to high-precision system-level applications such as multi-line integrated chips and high-resolution precision chips

Method used

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  • Clock regeneration delay chain with high precision and low kickback noise
  • Clock regeneration delay chain with high precision and low kickback noise
  • Clock regeneration delay chain with high precision and low kickback noise

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Embodiment 1

[0050] See figure 1 , figure 1 It is a schematic structural diagram of a clock regeneration delay chain with high precision and low kickback noise provided by an embodiment of the present invention, including:

[0051] A voltage conversion module, connected to the voltage input terminal, for converting the input signal into a first voltage signal and a second voltage signal;

[0052]A delay chain module, connected to the voltage conversion module and a clock input terminal, for controlling the clock delay time according to the first voltage signal and the second voltage signal to obtain a first clock signal cluster and a second clock signal cluster;

[0053] A clock driving module, connected to the delay chain module, is used for receiving and processing the first clock signal cluster and the second clock signal cluster, and outputting a multi-phase clock signal cluster.

[0054] In this embodiment, the voltage input signal VCTR is connected to the input terminal of the volt...

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Abstract

The invention discloses a clock regeneration delay chain with high precision and low kickback noise. The clock regeneration delay chain comprises a voltage conversion module which is connected with avoltage input end and is used for converting an input signal into a first voltage signal and a second voltage signal, a delay chain module which is connected with the voltage conversion module and a clock input end and is used for controlling clock delay time according to the first voltage signal and the second voltage signal to obtain a first clock signal cluster and a second clock signal cluster, and a clock driving module which is connected with the delay chain module and is used for receiving and processing the first clock signal cluster and the second clock signal cluster and outputting amulti-phase clock signal cluster. The clock regeneration delay chain provided by the invention has interference capability and clock regeneration capability and can adapt to high-precision system-level application.

Description

technical field [0001] The invention belongs to the technical field of laser radar signal receiver systems, and in particular relates to a clock regeneration delay chain with high precision and low kickback noise. Background technique [0002] Lidar uses a laser transmitter to emit laser light on the object to be detected. The laser echo reflected by the target object is received by the avalanche photodiode working in linear mode and converted into a current signal, and then the front-end analog receiver converts the avalanche photoelectric The pulse current generated by the diode is linearly converted into a voltage signal, and then the time-of-flight information of the pulse is obtained by using the time-to-digital conversion circuit, or the amplitude of the echo pulse is collected by the analog-to-digital converter, and finally provided to the subsequent digital signal processor for processing. further processing. In the time-to-digital conversion circuit, the delay chai...

Claims

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Application Information

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IPC IPC(8): G01S7/486G01S7/491G04F10/00
CPCG01S7/4865G01S7/4915G04F10/005
Inventor 朱樟明张玮马瑞刘马良王夏宇胡进
Owner XIDIAN UNIV
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