Inter-core communication method and device of multi-core processor
A multi-core processor and inter-core communication technology, applied in the field of inter-core communication methods and devices of multi-core processors, can solve the problems of time-consuming data copying, inter-core communication blocking, and reduced communication efficiency.
Active Publication Date: 2020-02-21
BEIJING HUAJIE IMI TECH CO LTD
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Problems solved by technology
This makes inter-core communication must wait for the completion of message processing, which can easily lead to inter-core communication congestion; in addition, when encountering a heavy load, data copying takes a long time, which greatly reduces communication efficiency
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[0056] The technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative work shall fall within the protection scope of the present invention.
[0057] The terms "first" and "second" in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish different objects, rather than to describe a specific sequence. In addition, the terms "including" and "having" and any variations of them are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is ...
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The invention discloses an inter-core communication method and device for a multi-core processor, and the method comprises: a transmitting core constructing to-be-processed data and storing the to-be-processed data in a target load region of a dynamic sharing region, the dynamic sharing region representing a region where effective loads are stored, and the effective loads representing effective data needing to be transmitted among multiple cores; constructing a load descriptor matched with the target load area, storing the load descriptor in a static sharing area, and the static sharing area representing an area used for storing a load queue descriptor and the load descriptor; and sending the interrupt signal to the receiving core, so that the receiving core obtains the load descriptor from the static sharing area after receiving the interrupt signal, and obtains the entry pointer of the target load area through the load descriptor, thereby realizing that the receiving core obtains theto-be-processed data from the target load area. Message transmission and message processing and decoupling are realized, the risk of inter-core communication congestion is greatly reduced, and the communication efficiency is improved.
Description
Technical field [0001] The present invention relates to the field of communication technology, in particular to a method and device for inter-core communication of a multi-core processor. Background technique [0002] With the continuous development of Internet of Things technology and the continuous catalysis of artificial intelligence technology, the requirements for chip functions and computing power are getting higher and higher. Traditional single-core chips are becoming more and more difficult to meet the demand, and the chips are developing in a multi-core and heterogeneous direction, which involves the communication problem between multi-processing cores. [0003] The existing multi-core communication scheme based on shared memory generally uses a pre-allocated fixed-size area as the load-sharing area, that is, the existing load-sharing area is implemented with a fixed-size queue, and message delivery and processing must be completed at the same time to complete once Inter...
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Login to View More IPC IPC(8): G06F15/173
CPCG06F15/17306
Inventor 古建中李骊
Owner BEIJING HUAJIE IMI TECH CO LTD