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Chip packaging structure and packaging method

A chip packaging structure and chip packaging technology, applied in electrical components, electrical solid devices, circuits, etc., can solve the problems of different packaging structures and packaging processes, inability to meet, small application range, etc., to achieve good overall performance and extended coupling resistance. effect of value

Inactive Publication Date: 2020-02-28
江苏中科智芯集成科技有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] Therefore, the technical problem to be solved by the present invention is that after solving the problem of fixing the pad size and the spacing between the pads of existing chips with a large number of pins, the requirements of different packaging structures and packaging processes cannot be met, and the application range is small. The problem

Method used

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  • Chip packaging structure and packaging method
  • Chip packaging structure and packaging method

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Experimental program
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Embodiment 1

[0039] This embodiment provides a fan-out chip packaging structure, such as figure 1 As shown, the package structure includes: a chip to be packaged, a silicon-based dielectric layer and an extension pad.

[0040] Among them, the chip to be packaged has multiple pads ( figure 1 Although only two pads are shown in FIG. 1, those skilled in the art should understand that there are multiple pads for the chip to be packaged).

[0041] Such as figure 1 As shown, the silicon-based dielectric layer 2 is provided on the device surface of the chip to be packaged 1, and a first groove 21 corresponding to the pad 11 of the chip to be packaged 1 is opened in the silicon-based dielectric layer 2, and the pad 11 passes through The first groove 21 is exposed outside the silicon-based dielectric layer 2. Here, the device surface of the chip to be packaged 1 immediately refers to the surface where the pad 11 of the chip to be packaged 1 is located. The silicon-based dielectric layer 2 is a thin film...

Embodiment 2

[0053] This embodiment provides a chip packaging method, and the packaging structure in Example 1 can be prepared according to this method and its preferred embodiments, and what has been described will not be repeated.

[0054] The chip packaging method provided in this embodiment, such as image 3 As shown, including the following steps:

[0055] S101: Provide chip 1 to be packaged. Here, the chip 1 to be packaged has multiple pads 11, Figure 4 Although only one pad 11 is shown in the figure, those skilled in the art should understand that there are multiple pads 11 of the chip 1 to be packaged.

[0056] S102: A silicon-based dielectric layer 2 is provided on the device surface of the chip 1 to be packaged. Such as Figure 4 As shown, a silicon-based dielectric layer 2 is provided on the device surface of the chip 1 to be packaged. The silicon-based dielectric layer 2 is a thin film layer that completely covers the device surface. Its thickness is usually several to tens of micro...

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Abstract

The invention discloses a chip packaging structure and a packaging method. The chip packaging structure comprises a to-be-packaged chip which is provided with a plurality of bonding pads, a silicon-based dielectric layer arranged on a device surface of the to-be-packaged chip, first grooves and extension bonding pads, wherein the first grooves corresponding to the bonding pads are formed in the silicon-based dielectric layer, the bonding pads are exposed out of the silicon-based dielectric layer through the first grooves, the extension bonding pads are in one-to-one correspondence with the bonding pads, the extension bonding pads fill the first grooves and extend out of the silicon-based dielectric layer, and the extension bonding pads are coupled with the bonding pads, and the cross sectional area of end parts, far away from the groove bottom of the first grooves, of the extension bonding pads is greater than or less than the groove bottom area of the first grooves. Based on the application of a silicon-based dielectric material, when the extension bonding pads are prepared, coupling between the extension bonding pads and the bonding pads can keep a relatively low contact resistance value, so overall electrical property of the packaging structure is ensured, by arranging the extension bonding pads coupled with the bonding pads in the first grooves, the size of the bonding padsof a packaged chip and the distance between the bonding pads can be adjusted.

Description

Technical field [0001] The present invention relates to the technical field of semiconductor integrated circuit packaging, in particular to a chip packaging structure and packaging method. Background technique [0002] Wafer-level fan-out packaging technology is gradually leading the development direction of advanced packaging technology by virtue of its advantages of high-density integration, light, thin and short, good heat dissipation performance and good high-frequency performance. Fan-out packaging technology realizes multi-chip system integration at the wafer level by reconstructing the wafer. The preparation method has developed from single-chip two-dimensional packaging to multi-chip three-dimensional integration. It is the most cost-effective advanced packaging method today. [0003] However, when packaging high-end chips, the number of chip pins is large, and some chips ensure that the pads have a certain size, and the spacing between the pads is small. When the chip is s...

Claims

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Application Information

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IPC IPC(8): H01L23/31H01L21/60
CPCH01L23/3157H01L24/81
Inventor 姚大平
Owner 江苏中科智芯集成科技有限公司
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