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Dual-substrate three-dimensional heterogeneous integrated chip and preparation method thereof

A technology for integrating chips and substrates, applied in the field of dual-substrate three-dimensional heterogeneous integrated chips and their preparation, can solve the problems of difficult application of new memory, limited speed and security of computing systems, etc., and achieves fast data exchange speed and increased difficulty. , the effect of low parasitic capacitance

Pending Publication Date: 2020-02-28
SHANGHAI INST OF MICROSYSTEM & INFORMATION TECH CHINESE ACAD OF SCI
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0005] This application is to solve the technical problems that the speed and security of the computing system in the prior art are limited, and the application of new memory is difficult

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  • Dual-substrate three-dimensional heterogeneous integrated chip and preparation method thereof
  • Dual-substrate three-dimensional heterogeneous integrated chip and preparation method thereof
  • Dual-substrate three-dimensional heterogeneous integrated chip and preparation method thereof

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Embodiment Construction

[0049]The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Apparently, the described embodiments are only some of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by persons of ordinary skill in the art without creative efforts fall within the protection scope of this application.

[0050] Reference herein to "one embodiment" or "an embodiment" refers to a specific feature, structure or characteristic that may be included in at least one implementation of the present application. In the description of the embodiments of the present application, it should be understood that the orientations or positional relationships indicated by the terms "upper", "lower", "top", and "bottom" are based on the orientations or positional relationships shown in the drawings...

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Abstract

The application provides a dual-substrate three-dimensional heterogeneous integrated chip and a preparation method thereof. The dual-substrate three-dimensional heterogeneous integrated chip includes:a first chip including a first substrate, a first active region layer, a first storage layer, a first metal layer, a first dielectric layer, and at least one first through hole, wherein the first substrate, the first active region layer, the first storage layer, the first metal layer, and the first dielectric layer are successively stacked and connected and the at least one first through hole isdisposed inside the first dielectric layer; a second chip including a second substrate, a second storage layer, a second dielectric layer, and at least one second through hole, wherein the second substrate, the second storage layer and the second dielectric layer are successively stacked and connected, at least one second through hole is disposed inside the second dielectric layer, and the first dielectric layer and the second dielectric layer are stacked and connected; and a conductive channel connecting the inside and the outside of the dual-substrate three-dimensional heterogeneous integrated chip, and used as an input end or an output end of the dual-substrate three-dimensional heterogeneous integrated chip.

Description

technical field [0001] The invention relates to the technical field of integrated circuits, in particular to a dual-substrate three-dimensional heterogeneous integrated chip and a preparation method thereof. Background technique [0002] Under the classic computer architecture, storage and computing are separated, which is reflected at the board level. Storage chips and computing chips are independently packaged on circuit boards, and data is exchanged through board-level wires. However, the board-level wires have large diameters and large parasitic capacitances, which limit the speed of data transmission; exposed wires allow attackers to eavesdrop on wire signals and obtain keys, which poses a great security risk. Three-dimensional integrated circuits (3D-ICs) using wafer-wafer stacking are expected to solve this problem. [0003] According to the speed, the storage architecture is static random access memory (Static Random-Access Memory, SRAM), dynamic random access memor...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L27/118H01L27/108H01L27/11H10B10/00H10B12/00
CPCH01L27/118H10B12/00H10B10/00
Inventor 雷宇宋志棠
Owner SHANGHAI INST OF MICROSYSTEM & INFORMATION TECH CHINESE ACAD OF SCI
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