Interface type IP system application verification platform and verification method

Abstract

The invention discloses an interface type IP system application verification platform and verification method. The method comprises the steps that a first verification IP module sends a verification instruction, receives response data of a second verification IP module and feeds back a register and interrupt information to a first virtual CPU for verification; the second verification IP module receives the verification instruction through a bus, executes the verification instruction and outputs response data, a feedback register and interrupt information to the second virtual CPU; the first virtual CPU controls the first verification IP module to send a verification instruction through the configuration channel, reads the register, the interrupt information and the state channel of the first verification IP module, and verifies whether the behavior of the first verification IP module and the behavior of the second verification IP module conform to expectation or not; and the second virtual CPU verifies whether the behaviors of the first verification IP module and the second verification IP module meet the expectation or not through the register and the interrupt information of thesecond verification IP module. Two independent chip systems are simulated to be interconnected, the master interface and the slave interface generate mutual excitation, the two independent chip systems are mutual simulation models and mutually matched for verification, and the verification efficiency is improved.

Description

Technical field [0001] The present disclosure relates to the field of IP verification technology, and in particular to an interface type IP system application verification platform and verification method. Background technique [0002] The statements in this section merely provide background information related to the present disclosure, and do not necessarily constitute prior art. [0003] Interface IP is an important part of SOC and ASIC systems, and an important module for data transmission and communication. The quality of its design is related to the function and performance of the entire chip system. However, due to the high complexity of the protocol involved and high timing requirements, the interface type IP has problems such as low verification efficiency, poor effect, and insufficient flexibility and convenience. [0004] The existing interface IP mainly includes controller interface IP (master interface IP) and device IP (slave interface IP). This type of IP generally ...

AI Technical Summary

Problems solved by technology

[0006] (1) System application verification needs to integrate various modules such as IO interface, CPU, and system bus to form a complete chip system. The system is complex and affects verification efficiency and simulation speed

(2) The interface protocol is complex, and the programming of the simulation model is difficult. It is necessary to purchase a simulation model or spend a lot of time programming and debugging the simulation model

(3) The simulation model has low flexibility, and cannot flexibly program and construct various abnormal scenarios

(4) The IP of the controller interface and the IP of the device interface are verified separately, and the workload is heavy, so they cannot verify each other

(5) Poor portability of driver code

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