Digital phase-locked loop frequency synthesizer

Abstract

The invention discloses a digital phase-locked loop frequency synthesizer based on a Fibonacci sequence time-to-digital converter. The digital phase-locked loop frequency synthesizer comprises a phasefrequency detector module, a time-to-digital converter TDC module, a proportional integral controller module, a digital control oscillator module and a frequency divider module. The TDC module is composed of t D triggers and a time delay unit. The D triggers directly output binary digital signals. Specifically, the output of the D flip-flop is multiplied by a corresponding Fibonacci coefficient fn, the delay units are multiplied by a corresponding delay time coefficient n = 1... T, and the value of t depends on the requirements of input reference frequency and output frequency. Compared witha TDC with a traditional structure, the TDC has the advantages that the number of required D triggers and delay units is greatly reduced, a decoder circuit is not required, and the chip area and powerconsumption are greatly reduced; the phase-locked loop can be locked, and the locking time is equivalent to that of a digital phase-locked loop based on a traditional structure TDC.

Description

technical field [0001] The invention relates to the technical field of digital phase-locked loops, in particular to a digital phase-locked loop frequency synthesizer based on a Fibonacci sequence time-to-digital converter. Background technique [0002] In a digital phase-locked loop frequency synthesizer, a time-to-digital converter (TDC, Time Digital Converter) is a very important module, which converts the phase difference information between an input reference clock signal and an output feedback clock signal into a digital signal. Generally, the detection range of phase difference is about 0-0.25π, which can meet the requirement of loop locking. If the phase difference signal detection range of TDC is 0-0.25π, then the detection of the phase difference signal within 0-0.25π is linear; if the phase difference signal exceeds 0.25π, the digital signal output by TDC and the phase difference signal are 0.25 When π, the corresponding digital signal is the same and does not cha...

AI Technical Summary

Problems solved by technology

[0004] It can be seen that the traditional constant resolution time-to-digital converter needs to occupy a considerable chip area and consume a large power consumption, which is not conducive to the low power consumption and low-cost integration requirements of the digital phase-locked loop frequency synthesizer

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