Manufacturing method of chip packaging structure

Abstract

The invention provides a manufacturing method of a chip packaging structure. The manufacturing method comprises the following steps: providing a slide and bonding a dielectric layer with a window on the slide; mounting a first chip on one side, deviating from the slide, of the dielectric layer, enabling the exposed unit of the first chip to correspond to the position of the window, and connectinga first conductive assembly to the first chip bonding pad of the first chip; mounting a second chip on one side, deviating from the slide, of the dielectric layer, and connecting a second conductive assembly and a third conductive assembly to the second chip bonding pad of the second chip so that the first chip and the second chip are electrically connected through the first conductive assembly and the second conductive assembly; manufacturing a plastic package body for packaging the first chip, the second chip, the first conductive assembly, the second conductive assembly and the third conductive assembly; and manufacturing a rewiring layer on the plastic package body to enable the second chip to be electrically connected with the rewiring layer through the third conductive assembly. Thefirst chip and the second chip are packaged together so that a shorter interconnection path, smaller parasitic inductance and lower loss are achieved, and high-bandwidth transmission is facilitated.

Description

technical field [0001] The invention relates to the technical field of chip packaging, in particular to a method for manufacturing a chip packaging structure. Background technique [0002] The package not only plays the role of mounting, fixing, sealing, protecting the chip and enhancing the electrothermal performance, but also realizes the connection between the internal chip and the external circuit. Specifically, the pads on the chip are connected to the pins of the package shell with wires These pins are connected to other devices through wires on the printed circuit board. The bare chip refers to the product form before the semiconductor integrated circuit chip is manufactured and packaged. In order to increase the reliability and connection stability of the chip, most bare chips are pre-packaged at present. However, some types of chips have exposed units that need to interact with the external environment. For example, there are optical interfaces on optical chips for...

AI Technical Summary

Problems solved by technology

[0004] Therefore, the technical problem to be solved by the present invention is to overcome the long chip distance when the chip with the exposed unit is interconnected with other chips in the prior art, the electrical interconnection path is long, the loss is large during the transmission of electrical signals, and the chip is not packaged. The defects of poor reliability and short service life provide a method for manufacturing a chip packaging structure

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