Chip packaging method

Abstract

The invention discloses a chip packaging method. The chip packaging method comprises the following steps: S01, bonding a wafer and a glass wafer; S02, cutting the bonded wafer into N chips, wherein Nis a positive integer larger than 0, and each chip comprises a working area and a bonding pad; S03, cutting the bonded glass wafer into N packaging layers in one-to-one correspondence with the N chips; and S04, removing the packaging layers on the bonding pad and leading out the bonding pad. According to the chip packaging method provided by the invention, the wafer is firstly packaged and then back-cut such that the working performance of the packaged chip is not influenced, and the service life of the chip can be prolonged.

Description

technical field [0001] The invention relates to the field of chip packaging, in particular to a chip packaging method. Background technique [0002] Chip packaging is a casing for mounting semiconductor integrated circuit chips, which has the functions of placing, fixing, sealing, protecting the chip and enhancing the electrical and thermal performance. The chip package is a bridge between the internal world of the chip and the external circuit. The contacts of the chip are connected to the bonding pads of the package shell with wires, and the bonding pads are connected to other devices through the wires on the printed board. [0003] For the CIS chip, during the packaging process, it is also necessary to ensure that the packaging layer does not affect the photosensitive performance of the photosensitive area in the CIS chip. Therefore, the packaging of the CIS chip should not only consider the packaging efficiency, but also consider the protection of the photosensitive are...

AI Technical Summary

Problems solved by technology

[0004] The structure of the packaged CIS chip prepared by the above method is as attached figure 2 As shown, the above packaging method has the following defects: (1) due to the use of the DAM adhesive layer to bond the CIS chip and the packaging layer, the DAM adhesive layer uses a high-viscosity opaque adhesive, which is prone to overflow glue during the bonding process. Glue will stain the photosensitive area in the CIS chip

(2) In the prior art, the DAM adhesive layer is coated around the photosensitive area in the CIS chip, thereby creating a cavity between the encapsulation layer and the CIS chip, and the existence of the cavity makes it easy for the CIS chip to be tested in the subsequent airtightness test. If the airtightness of the CIS chip is not good, it will not only cause degumming of the CIS chip in the subsequent use process, but also affect the light sensitivity of the photosensitive area of ​​the CIS chip, thus affecting the use effect and life of the CIS chip

(3) In the prior art, the bonding pad in the CIS chip is usually led out by welding, which requires multiple welding processes, which is cumbersome

(4) In the prior art, in steps S02 and S03, during the bonding pad lead-out and bonding process, particulate impurities in the environment may be introduced. Once the impurities are packaged in the CIS chip, they will appear in the image generated by the CIS due to The black spots caused by the introduction of impurities affect the imaging effect of CIS

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