A logic implementation method based on bipolar memristor
An implementation method and bipolar technology, applied in the direction of instruments, static memory, digital memory information, etc., can solve the problems of increasing the number of steps, the number of operation steps are too many, and it is impossible to directly perform logical cascades, etc. few effects
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Embodiment 1
[0051] figure 1 For the used bipolar memristor of logic implementation method of the present invention, T 1 is the top electrode, T 2 As the bottom electrode, there are two resistance states with stable transitions. When implementing the AND logic function, the initial state of the device is used as the input p, T 1 Terminal voltage as input q, end-state resistance as output, T 2 The end is placed at a high voltage Vreset, as long as one of p and q is "0", the output end-state resistance is "0". Experimental results such as figure 2 As shown in (a); when implementing the OR logic function, the initial state of the device is used as the input p, T 1 Terminal voltage as input q, end-state resistance as output, T 2 Put the terminal at 0 voltage, as long as one of p and q is not "0", the output end-state resistance will be "1". The experimental results are as follows figure 2 As shown in (b); when implementing XOR logic, the initial state of the device is used as the inpu...
Embodiment 2
[0053] A one-bit full adder is realized based on the logic implementation method of the present invention, and the one-bit full adder implementation scheme of the present invention only needs three devices and six steps of operation. The full adder structure is as image 3 As shown, the top electrodes of the three devices are respectively connected to SL(1), SL(2), and SL(3), and the bottom electrodes are respectively connected to BL(1), BL(2), and BL(3). For a full adder, the three input variables are the addend A, the summand B, and the carry C from the lower bit. i , the two output variables are the original bit and S and the carry C to the high bit o , the logical expression is as follows:
[0054]
[0055]
[0056] The operation method is that the first step is to write data A in devices 1, 2, and 3; the second step is to read the resistance values of devices 1 and 2; the third step is to use the read resistance values of devices 1 and 2 as selection signals t...
Embodiment 3
[0061] The two-bit multiplier is realized based on the logic implementation method of the present invention, and the two-bit multiplier implementation scheme of the present invention only needs five devices and six steps of operation. The structure of the two-bit multiplier is as follows Figure 5 As shown, the top electrodes of five devices are respectively connected to SL(1), SL(2), SL(3), SL(4), and SL(5), and the bottom electrodes are respectively connected to BL(1), BL(2) , BL(3), BL(4), BL(5). Define the two-bit multiplier input as A 1 A 0 , B 1 B 0 , the output is P 4 P 3 P 2 P 1 , and the calculation results are stored in devices 1, 2, 3, and 4. The logical expression of the two-bit multiplier is as follows:
[0062] P 1 =A 0 B 0 (3)
[0063]
[0064]
[0065] P 4 =A 1 A 0 B 1 B 0 (6)
[0066] The method of operation is the first step to write A in device 1, 4, 5 0 ; In the second step, device 1 does A 0 B 0 operation, device 3 is written...
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