Semiconductor structure and forming method thereof

Abstract

The invention discloses a semiconductor structure and a forming method thereof. The forming method comprises the following steps of forming a substrate, wherein the substrate comprises a PMOS region,a substrate and semiconductor columns protruding out of the substrate, the semiconductor columns of the PMOS region comprise a first semiconductor column and a second semiconductor column located on the first semiconductor column, and the molar volume percentage of Ge in the second semiconductor column is larger than the molar volume percentage of Ge in the first semiconductor column; forming a PMOS drain region in the bottom of the first semiconductor column in the PMOS region; after the PMOS drain region is formed, forming a gate structure surrounding the semiconductor column, wherein the gate structure of the PMOS region covers the junction of the first semiconductor column and the second semiconductor column and exposes the top of the second semiconductor column, and the semiconductorcolumn covered by the gate structure is used as a channel layer; and after the gate structure is formed, forming a PMOS source region in the top of the second semiconductor column. The embodiment of the invention is beneficial to improving the stability of a PMOS transistor, such as a hot carrier effect, a spontaneous heating effect, etc.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a semiconductor structure and a forming method thereof. Background technique [0002] With the rapid development of semiconductor manufacturing technology, semiconductor devices are developing towards higher component density and higher integration, and the development trend of semiconductor process nodes following Moore's Law continues to decrease. Transistors, as the most basic semiconductor devices, are currently being widely used. Therefore, with the increase of component density and integration of semiconductor devices, in order to adapt to the reduction of process nodes, the channel length of transistors has to be continuously shortened. [0003] The shortening of the channel length of the transistor has the advantages of increasing the die density of the chip and increasing the switching speed. However, with the shortening of the channel length, the distance bet...

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Problems solved by technology

However, with the shortening of the channel length, the distance between the source and the drain of the transistor is also shortened, and the control ability of the gate to the channel becomes worse, resulting in the phenomenon of subthreshold leakage, the so-called short channel The short-channel effects (SCE) are more likely to occur, and the channel leakage current of the transistor increases

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