Digital low dropout regulator

Abstract

The invention belongs to the field of voltage stabilizers, the invention relates to a voltage stabilizer and particularly relates to a digital low-dropout voltage stabilizer. The stabilizer comprisesa voltage input end, a voltage output end, a first reference voltage input end, a second reference voltage input end, a third reference voltage input end, a voltage comparator, a transient detector, acoarse adjustment controller, a fine adjustment controller, a first transistor array, a second transistor array and a load capacitor. The stabilizer is advantaged in that a method of combining coarseadjustment and fine adjustment is adopted so that the transient response speed and precision are improved.

Description

technical field [0001] The invention belongs to the field of voltage regulators, and in particular relates to a digital low-dropout voltage regulator. Background technique [0002] With the continuous decline of process size, system-on-chip has become the mainstream of integrated circuit design due to its advantages of low power consumption, high efficiency, and small area. Part of it plays a vital role in the performance of the whole system, and it is of great significance to study on-chip integrated LDO with fast transient response. [0003] Traditional LDOs are analog LDOs that are regulated with high-gain error amplifiers. They have the advantages of high bandwidth, low ripple, fast transient response, and high power supply rejection ratio, making them suitable for applications that are sensitive to power rail noise, such as analog circuits and radio frequency circuits. But at the supply voltage close to the sub-threshold, there is not enough voltage margin to make the...

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Problems solved by technology

Since this structure does not use a clock signal, it greatly reduces power consumption and enhances transient response, but the delay

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