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LDPC coding and decoding method and system

A technology of encoding, decoding and encoding, which is applied in the field of LDPC encoding and decoding methods and systems, can solve problems such as communication interruption or occupying too many logic resources, and achieve the effects of improving adaptability and flexibility, saving logic resources, and avoiding communication interruption

Pending Publication Date: 2020-05-29
SHENZHEN AEROSPACE INNOTECH +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

For this reason, the present invention proposes an LDPC encoding and decoding method, which can solve the problem of communication interruption or occupying more logic resources in the current LDPC encoding and encoding reconfiguration process to a certain extent

Method used

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  • LDPC coding and decoding method and system
  • LDPC coding and decoding method and system
  • LDPC coding and decoding method and system

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Embodiment 1

[0044] Embodiment 1 of the present invention provides an LDPC encoding and decoding method. To a certain extent, it is used to solve the problem of communication interruption or occupying more logic resources during the current LDPC codec reconfiguration process. The partial reconfigurable function of FPGA is used to realize the LDPC codec function of different code lengths, while avoiding reconfiguration. Conserve FPGA logic resources while communication interruption occurs. LDPC code is a block error-correcting code with a sparse parity check matrix, which is suitable for almost all channels. Its performance is close to the Shannon limit, and its description and implementation are simple, easy to carry out theoretical analysis and research, and the decoding process is simple and feasible. Parallel operation, suitable for hardware implementation.

[0045] figure 1 A schematic flow chart of an LDPC encoding and decoding method provided by an embodiment of the present inventi...

Embodiment 2

[0090] This embodiment provides an LDPC encoding and decoding system for executing the method described in Embodiment 1, such as image 3 As shown, it is a structural block diagram of a kind of LDPC encoding and decoding system of the present embodiment, including:

[0091] Building a reconfigurable unit 100: used to build reconfigurable modules corresponding to different code lengths, the reconfigurable modules include: LDPC encoding reconfigurable modules or LDPC decoding reconfigurable modules;

[0092] Creating a reconfigurable partition unit 200: used to create a physically constrained area as a reconfigurable partition, and set a reconfigurable module for each reconfigurable partition;

[0093] Wiring design unit 300: for performing wiring design of each reconfigurable partition;

[0094] Execution unit 400: used to create a bit stream for each reconfigurable partition after the wiring design is completed, and run the bit stream on the FPGA to perform LDPC encoding or L...

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Abstract

The invention discloses an LDPC coding and decoding method and system, and relates to the field of communication. The method comprises the steps: constructing reconfigurable modules corresponding to different code lengths, wherein the reconfigurable modules comprise an LDPC coding reconfigurable module or an LDPC decoding reconfigurable module; then, creating a physical constraint region as a reconfigurable partition, setting a reconfigurable module for each reconfigurable partition, carrying out wiring design on each reconfigurable partition, establishing a bit stream for each reconfigurablepartition after the wiring design is completed, and running the bit stream on the FPGA to carry out LDPC encoding or LDPC decoding. The LDPC encoding and decoding process based on the reconfigurable FPGA is realized; according to different communication reliability requirements, different LDPC coding code lengths are converted on hardware, and LDPC coding and decoding functions with different codelengths are realized by utilizing a partial reconfiguration function of the FPGA, so logic resources of the FPGA are saved while communication interruption caused by reconfiguration is avoided, and the adaptability and the flexibility of a satellite channel coding process are improved.

Description

technical field [0001] The invention relates to the communication field, in particular to an LDPC encoding and decoding method and system. Background technique [0002] With the continuous advancement of communication technology, people have higher and higher requirements on the quality of wireless communication. For example, the communication quality can be improved by integrating the terrestrial network and the satellite network. However, in this scenario, how the satellite channel coding can cope with the changing and harsh channel environment is the main technical challenge to be faced. For example, the common LDPC code adopts the method of changing the length of the code word in the face of poor satellite channel conditions, or improves the error correction capability by changing the decoding algorithm, but in general, the decoding algorithm adopts an algorithm suitable for hardware operation. The cost of easy change is high. [0003] For general FPGAs, there are two ...

Claims

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Application Information

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IPC IPC(8): H03M13/11
CPCH03M13/1105
Inventor 闫泽涛冯汉炯李德志
Owner SHENZHEN AEROSPACE INNOTECH
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