Cascading method of full-interconnection AXI bus

Abstract

The invention relates to a cascading method of a full-interconnection AXI bus, under the condition that signals are not increased, a cascading central unit analyzes channel transmission in a subsystemcorresponding to signal gating, key path delay in the AXI system bus is shortened, and the time sequence convergence difficulty of a full-interconnection system is reduced. Due to the fact that eachAXI subsystem carries out independent arbitration and corresponds to different system environments, arbitration priority vectors of each host end and each slave end in the subsystems can be flexibly configured, and independence and flexibility of a system bus are guaranteed. Each AXI subsystem realizes N-M full interconnection, so that host ends in different subsystems are supported to simultaneously initiate read-write operation at the same moment, the parallel communication capability is supported, and the bandwidth and the transmission efficiency of a system bus are improved. The subsystemsare independent of one another, master machines and slave machines in the subsystems are independent of one another, plugging of the subsystems and the increase and decrease of the master machines and the slave machines do not influence the original system architecture, and system cascading is more convenient.

Description

technical field [0001] The invention relates to the technical field of AXI bus, in particular to a cascading method of fully interconnected AXI bus. Background technique [0002] AXI (Advanced eXtensible Interface) is a bus protocol. This protocol is the most important part of the AMBA (Advanced Microcontroller Bus Architecture) 3.0 protocol proposed by ARM. It is an on-chip bus for high performance, high bandwidth, and low latency. . Its address / control and data phases are separated, and it supports unaligned data transmission. At the same time, in burst transmission, only the first address is needed, while separate read and write address channels, and supports significant transmission access and out-of-order access. AXI is a new high-performance protocol in AMBA. AXI technology enriches the existing AMBA standard content to meet the needs of ultra-high performance and complex system-on-chip (SoC) design. With the sharp increase in chip complexity, the AXI system bus fac...

AI Technical Summary

Problems solved by technology

AXI's fully interconnected bus architecture allows transmission paths between multiple masters and multiple slaves to exist in the system at the same time, but with the gradual expansion of the system scale, the number of masters and slaves increases exponentially, and the timing convergence of the system design becomes a limitation Problems with system performance

In order to make the system run at a high frequency, the form of full interconnection can only be given up. The system bus is shared by multiple MASTER master devices, and multiple MASTER master devices can initiate read and write operations at the same time. The arbitrator in the system bus is responsible for arbitrating the commands of the MASTER master devices. , authorize the bus to the corresponding MASTER through blanking, and send the command to the corresponding SLAVE slave device, but on the one hand, it is impossible to realize simultaneous communication of multiple MASTER master devices, and this serial access mechanism limits the bandwidth and transmission efficiency of the system bus; On the other hand, since the system bus address resources cannot be expanded wirelessly with the increase of host ports, nor can the bus architecture be changed arbitrarily as the requirements change, which reduces the scalability and reusability of the system bus

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