Looking for breakthrough ideas for innovation challenges? Try Patsnap Eureka!

Parallel test system for multi-channel intermittent disconnection faults based on fpga

A technology for disconnecting faults and testing systems. It is applied in the direction of electronic circuit testing, measuring electricity, and measuring devices. It can solve problems such as lack of testing methods, high testing missed detection rate, and low efficiency, so as to avoid missed testing and save testing resources. , Improve the effect of testing difficulties

Active Publication Date: 2022-03-25
NAT UNIV OF DEFENSE TECH
View PDF4 Cites 0 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0015] The purpose of this application is to provide a new FPGA-based parallel test system for multi-channel intermittent disconnection faults in view of the lack of multi-channel intermittent disconnection fault detection means, high test missed detection rate and low efficiency in complex electronic equipment. It makes it possible to cover the intermittent faults of many connection links in electronic equipment with a small intermittent fault test module path, realize the synchronous parallel testing of multiple intermittent disconnection faults, and avoid missed detection at the same time

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Parallel test system for multi-channel intermittent disconnection faults based on fpga
  • Parallel test system for multi-channel intermittent disconnection faults based on fpga
  • Parallel test system for multi-channel intermittent disconnection faults based on fpga

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0033] In order to more clearly understand the above objects, features and advantages of the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that the embodiments of the present application and the features of the embodiments may be combined with each other in the case of no conflict.

[0034] In the following description, many specific details are set forth to facilitate a full understanding of the present application. However, the present application can also be implemented in other ways different from those described herein. Therefore, the protection scope of the present application is not subject to the following disclosure. Restrictions to specific embodiments.

[0035] like figure 1As shown, this embodiment provides an FPGA-based multi-channel intermittent disconnection fault parallel test system, which is suitable for the intermittent disconnec...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

This application discloses a multi-channel intermittent disconnection fault parallel test system based on FPGA, which is suitable for detecting and diagnosing intermittent disconnection faults of multiple connection links in electronic equipment. The system includes: a voltage coupling module set at the detection end of the system , the voltage coupling module includes a plurality of coupling sub-modules, any coupling sub-module includes a first resistor and a second resistor connected in parallel, one end of the first resistor is connected in parallel with the second resistor and then connected to the detection end, and the other end of the first resistor is connected to At the low level end of the system, the other end of the second resistor is connected to the output end of the coupling sub-module, and the coupling sub-module is used to transmit the voltage signal of the second resistor to the signal processing module; the signal processing module is used to judge that the voltage signal is less than When the fault voltage threshold is exceeded, it is determined that intermittent disconnection faults have occurred in the connection link. Through the technical solution in this application, the parallel detection of intermittent faults in multiple connection links is realized, which helps to improve the problems of difficulty in testing intermittent faults and incomplete test coverage.

Description

technical field [0001] The present application relates to the technical field of fault detection, and in particular, to an FPGA-based parallel testing system for intermittent disconnection of multiple channels. Background technique [0002] Intermittent disconnection failure is the sudden change of the equipment after long-term vibration, temperature and other environmental stress and load stress and other long-term effects, reaching a certain degradation state, and being subjected to real-time strong vibration, thermal radiation and other high stress during service. A connection-type fault of very short duration. Its essence is the coupling effect between the damage state of the connection link and the real-time stress under the long-term action of multiple stresses. [0003] In electronic equipment, the connection link is usually used as an important signal transmission channel, and the reasons for the intermittent disconnection failure are as follows: [0004] (1) The v...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Patents(China)
IPC IPC(8): G01R31/28
CPCG01R31/2812
Inventor 刘冠军李华康吕克洪邱静张勇杨鹏吴晓龙程先哲祝尊卿
Owner NAT UNIV OF DEFENSE TECH
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Patsnap Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Patsnap Eureka Blog
Learn More
PatSnap group products