Manufacturing method of MTP device and MTP device

A manufacturing method and device technology, applied in the direction of electric solid devices, semiconductor devices, electrical components, etc., can solve the problems of reducing the area of ​​MTP devices

Pending Publication Date: 2020-06-12
SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0005] The object of the present invention is to provide a manufacturing method of an MTP device and an MTP device, to solve the problem that the area of ​​the MTP device is also reduced while increasing the erasing voltage of the MTP device

Method used

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  • Manufacturing method of MTP device and MTP device
  • Manufacturing method of MTP device and MTP device
  • Manufacturing method of MTP device and MTP device

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Embodiment Construction

[0040]The manufacturing method of the MTP device and the MTP device proposed by the present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer from the following description. It should be noted that all the drawings are in a very simplified form and use imprecise scales, and are only used to facilitate and clearly assist the purpose of illustrating the embodiments of the present invention. In addition, the structures shown in the drawings are often a part of the actual structures. In particular, each drawing needs to display different emphases, and sometimes uses different scales.

[0041] The present invention provides a kind of manufacturing method of MTP device, with reference to figure 2 , figure 2 The schematic flow chart of the manufacturing method of the MTP device of the embodiment of the present invention, the MTP devic...

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Abstract

The invention provides a manufacturing method of an MTP device. The manufacturing method comprises the following steps: firstly, forming a substrate comprising a programming region substrate and an erasing region substrate; forming a well region in the programming region substrate; forming an ion drift region in the erase region substrate; sequentially forming a gate oxide layer and a floating gate layer on the substrate; and performing lightly doped drain injection on the ion drift region to form a shallow junction. Furthermore, the invention also provides an MTP device which comprises a substrate, a gate oxide layer and a floating gate layer, the substrate comprises a programming region substrate and an erasing region substrate, the well region is formed in the programming region substrate, an ion drift region is formed in the erasing region substrate, and a shallow junction is formed in the erasing region substrate. An ion drift region is formed in the substrate of the erase region,and a shallow junction is formed on the substrate of the erase region, so that the charge capacity of the formed shallow junction can be further increased, the voltage withstanding performance of theshallow junction is improved, and the erase voltage of the MTP device is improved under the condition that the area of the MTP device is reduced.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a method for manufacturing an MTP device and the MTP device. Background technique [0002] A MTP device (Multiple Programmable Non-Volatile Memory Device) is a reusable device that allows users to program, erase, modify or design it multiple times. [0003] refer to figure 1 , figure 1 is a schematic diagram of the MTP device in the prior art, from figure 1 It can be seen that the MTP is generally divided into a programming area 1 and an erasing area 2, and an MTP device generally includes: a substrate 10, a gate oxide layer 20 on the substrate, and a floating gate layer on the gate oxide layer 20 30 , a shallow trench isolation structure 11 is formed in the substrate 10 , and the substrate 10 generally includes a programming region substrate 101 and an erasing region substrate 102 . A first well region 12 (such as an N well) is usually formed in the progr...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L27/11521
CPCH10B41/30
Inventor 令海阳
Owner SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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