Lateral inhibitory neuron circuit based on ferroelectric transistor FEFET

Abstract

The present invention proposes a side-inhibition neuron circuit based on a ferroelectric transistor FeFET, which includes a capacitor, a reset tube, a positive feedback tube, two-stage series inverters, and a ferroelectric transistor; wherein, the capacitor is used to simulate biological The cell membrane capacitance of the neuron accumulates the charge brought by the input post-synaptic current; the reset tube is an N-type MOSFET device that provides a reset path for the charge accumulated on the capacitor; the positive feedback tube is a P-type MOSFET device, When the input of the first-stage inverter is close to its logic threshold level, it replenishes the charge for the capacitor; the two-stage series inverter is composed of two sets of complementary CMOS, which amplifies the voltage change at the input terminal, and the pulse is generated at its output terminal. ; The ferroelectric transistor is an N-type FeFET device used to mimic the lateral inhibition function of biological neurons. The invention can significantly reduce the hardware overhead; meanwhile, it highly simulates the basic characteristics and advanced functions of biological neurons.

Description

technical field [0001] The invention relates to the physical realization of side-inhibitory neurons in neuromorphic computing, in particular to a side-inhibition neuron circuit based on ferroelectric transistor FeFET. Background technique [0002] With the vigorous development of information technology, human society has entered the era of "data explosion", and the annual exponential growth of data volume has brought unprecedented pressure on data processing and calculation. Due to the characteristics of the traditional von Neumann computing architecture, which separates storage and computing, the transmission of data between the storage unit and the computing unit will cause a lot of waste of power consumption and energy consumption. In today's information society and even the intelligent society, there is a huge amount of data In this context, this problem will become more and more serious. [0003] Inspired by the computing model of the human brain, the researchers propo...

AI Technical Summary

Problems solved by technology

At present, in terms of the hardware implementation of neuromorphic computing, many research institutions and enterprises have developed a variety of neuromorphic chips. Mainly based on traditional CMOS circuit construction, there are problems such as large hardware overhead and high circuit energy consumption, which is not conducive to high-density and large-scale integration, and may cause the network to lose the original power consumption and energy consumption advantages brought by the architecture level

In addition, advanced biological neuron functions such as lateral inhibition may affect the realization of the brain-like function of the entire spiking neural network. However, the implementation based on traditional CMOS circuits often requires the introduction of significant additional hardware overhead.

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