A Secure Coprocessor Structure Based on RISC-V Instruction Extension

Abstract

The invention discloses a safety coprocessor structure based on RISC-V instruction extension, a special instruction execution unit and a general instruction execution unit are respectively connected to the output result control, and the safety instruction coding logic given by the mainstream pipeline decoding stage of the processor is based on The instruction code is decoded in detail and the instruction is sent to the special instruction execution unit or the general instruction execution unit. After the instruction is executed, the operation result is output to the write-back stage of the main pipeline of the processor through the output result control logic, which is realized by the main pipeline of the processor. Write-back operations for general-purpose registers. The invention not only avoids the problem of instruction set authorization, but also effectively reduces the intrusion to the original processor, and expands the scope of application of encryption and decryption algorithms, and has high application value.

Description

technical field [0001] The invention belongs to the technical field of integrated circuit design and processor design, and in particular relates to a safety coprocessor structure based on RISC-V instruction extension. Background technique [0002] Military applications, represented by aerospace applications, are facing more and more serious threats to information security. Malicious attackers can use various means to monitor core electronic systems, thereby achieving the purpose of stealing or tampering with key military information. At present, most of the instructions and data of embedded systems are stored in external SRAM or DRAM, so by adding a small amount of hardware changes to the circuit board, the interception of data on the storage bus can be completed, and even the data modification can be reversed. Based on this practical requirement, both the program and data in the off-chip memory need to be encrypted, which requires the processor to be able to decode the prog...

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Problems solved by technology

[0004] (1) "Standard instruction + bus IP", this solution is the simplest to implement in hardware, such as "Coprocessor for Encryption and Decryption Process Control" published by Wang Jianfei et al. The standard bus interface can be integrated into the processor system naturally. At the same time, since it does not involve the modification of the instruction set, there is no need to modify the compiler. However, there is a performance bottleneck in this structure, mainly due to the control of IP and the original text / encryption The transmission of files must be controlled by the processor, and each operation must pass through the system bus, and the efficiency is often not as expected;

[0005] (2) "Instruction extension + custom execution unit", this form is to customize and modify the processor from the bottom layer. First, the instruction is extended based on the commercial instruction set, and then the corresponding execution unit is designed at the execution level of the pipeline. From the software point of view, the method involves the authorization of commercial instruction sets, and from the hardware point of view, the substantial modification of the pipeline will cause the adequacy of the verification coverage. Customized design of an encryption algorithm, which is poor in versatility and universality;

[0006] (3) "Instruction extension + coprocessor" also performs instruction extension on the basis of commercial instruction sets, but it does not modify the original processor pipeline structure, but integrates an independent acceleration engine outside the pipeline, because it does not change the mainstream pipeline structure, so the functional complexity is lower, but there are still issues of authorization and universality

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