Memory and forming method thereof, and memory cell array and driving method thereof

[0045] As mentioned in the background art, the performance of flash memory is poor.

[0046] The reasons for the problem will be explained below in conjunction with the drawings.

[0047] figure 1 It is a schematic diagram of a memory cell array.

[0048] A memory cell array, please refer to figure 1 , Including: a semiconductor substrate 100, the semiconductor substrate 100 includes: a number of parallel and separate active regions 110 arranged in a second direction Y, and an isolation structure surrounding the active region 110 (not shown in the figure) The active area 110 extends along the first direction X. In the first direction X, each active area 110 includes a plurality of memory cell areas, and each memory cell area includes: a storage area A and a storage area located in the storage area. A source region B and a drain region C on both sides of A; several source regions, and one source region B has one source region; several drain regions (not shown in the figure), and one drain region There is a drain region in B; a plurality of first bit lines 131 and second bit lines 132 arranged in parallel, the first bit lines 131 and the second bit lines 132 are respectively located on adjacent active regions 110, the first The bit line 131 is electrically connected to the source area on the same column, the second bit line 132 is electrically connected to the source area on the same column, and the first bit line 131 extends along the first direction X, the second bit The line 132 extends along the first direction X; a plurality of third bit lines 133 arranged in parallel, the third word line 133 is located between the adjacent first bit line 131 and the second bit line 132, and the third bit The line 133 is electrically connected to two adjacent drain regions, and the third bit line 133 extends along the first X direction.

[0049] figure 2 Is a cross-sectional schematic diagram of a flash memory, and figure 2 for figure 1 A schematic cross-sectional view along the X-X1 tangent direction.

[0050] A kind of flash memory, please refer to figure 2 , Including: a semiconductor substrate 100, the semiconductor substrate 100 includes: a storage area A and a source area B and a drain area C located on both sides of the storage area A, the source area B and the drain area C Respectively adjacent to the storage area A; the first storage unit 141, the second storage unit 142 located on the storage area A, and the word line grid located between the first storage unit 141 and the second storage unit 142 143; a source region 151 located in the source region B; a drain region 152 located in the drain region C; a first plug 161 located on the source region 151, and the first plug 161 Is electrically connected to the source region 151; a second plug 162 located on the drain region 152, and the second plug 162 is electrically connected to the drain region 152.

[0051] In the above-mentioned memory cell array, in the memory cells adjacent in the second direction Y, the first bit line 131 and the second bit line 132 need to be electrically connected to the source regions 151 in the two memory cells, and the third bit line is required 133 is commonly electrically connected to the drain region 152 in the two memory cells. It can be seen that at present, for every two adjacent active regions, three metal lines are required, that is, the first bit line 131, the second bit line 132, and the third bit line 133 lead out two memory cells. Therefore, one The size of the active region period requires 1.5 metal line periods. Since the size of the metal line period is limited by the limitations of the existing photolithography, the size of the metal line period cannot be reduced, and the size of one active area period cannot be reduced. Therefore, it is not conducive to reducing the density of the memory cell array.

[0052] In order to solve the technical problem, an embodiment of the present invention provides a method for forming a memory, including: providing a substrate, the substrate including a first storage area and a second storage area that are adjacent and separated; in the first storage area A first storage structure is formed on the upper surface. The first storage structure includes: a first storage unit and a second storage unit, and a first word line gate located between the first storage unit and the second storage unit; A second storage structure is formed on the storage area, and the second storage structure includes: a third storage unit and a fourth storage unit, and a second word line grid located between the third storage unit and the fourth storage unit; forming the After the first storage structure and the second storage structure, a source area is formed in the substrate between the first storage area and the second storage area; after the source area is formed, in the first storage area and the second storage area A first drain region and a second drain region are formed in the substrate on both sides of the region. The memory formed by the method can reduce the distance between two pairs of memory cells, thereby increasing the density of the memory, and at the same time, it is beneficial to the reasonable layout of the memory cell array, thereby increasing the density of the memory cell array.

[0053] In order to make the above-mentioned objectives, features and beneficial effects of the present invention more obvious and understandable, specific embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings.

[0054] Figure 3 to Figure 17 It is a schematic cross-sectional view of each step of a memory forming method in an embodiment of the present invention.

[0055] Please refer to image 3 , A substrate 200 is provided, and the substrate 200 includes a first storage area I and a second storage area II that are adjacent and separated.

[0056] In this embodiment, the material of the substrate 200 is silicon; in other embodiments, the material of the substrate can also be germanium, silicon germanium, silicon carbide, gallium arsenide, or indium gallium; in other embodiments Here, the base may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate.

[0057] Next, a first storage structure is formed on the first storage area I. The first storage structure includes a first storage unit and a second storage unit, and a first storage unit located between the first storage unit and the second storage unit. A word line gate; a second storage structure is formed on the second storage area II, the second storage structure includes: a third storage unit and a fourth storage unit, and located between the third storage unit and the fourth storage unit The second word line grid between.

[0058] In this embodiment, the first storage structure and the second storage structure are formed in the same process.

[0059] In this embodiment, the method for forming the first storage structure further includes: forming a first sidewall on the top surface of the first storage unit and the top surface of the second storage unit; and the method for forming the second storage structure further The method includes forming a second side wall on the top surface of the third storage unit and the top surface of the fourth storage unit.

[0060] Please refer to Figure 4 , Forming a memory cell material film on the surface of the first storage area I and the second storage area II.

[0061] The memory cell material film provides material for subsequent formation of the first memory structure and the second memory structure.

[0062] The memory cell material film includes: a floating gate dielectric film 211; a floating gate electrode film 212 on the surface of the floating gate dielectric film 211; a control gate dielectric film 213 on the surface of the floating gate electrode film 212; The gate electrode film 214 on the surface of the gate dielectric film 213 is controlled.

[0063] Specifically, in this embodiment, the floating gate dielectric film 211 is located on the surface of the substrate 200 between the first storage area I and the second storage area II, and the surface of the substrate 200 between the first storage area I and the second storage area II. , And the surface of the substrate 200 on both sides of the first storage area I and the second storage area II.

[0064] The material of the floating gate dielectric film 211 includes silicon oxide, silicon nitride, silicon carbide nitride, silicon nitride boride, silicon oxynitride, or silicon oxynitride. In this embodiment, the material of the floating gate dielectric film 211 is silicon oxide.

[0065] The material of the floating gate electrode film 212 includes polysilicon or metal. In this embodiment, the material of the floating gate electrode film 212 is polysilicon.

[0066] The material of the control gate dielectric film 213 includes: silicon oxide, silicon nitride, silicon oxynitride, silicon nitride boride, silicon oxynitride, or silicon oxynitride. In this embodiment, the control gate dielectric film 213 has a three-layer structure of silicon oxide-silicon nitride-silicon oxide.

[0067] The material of the control gate electrode film 214 includes polysilicon or metal. In this embodiment, the material of the control gate electrode film 214 is polysilicon.

[0068] Please refer to Figure 5 A mask layer 220 is formed on the surface of the memory cell material film. The mask layer 220 has a first groove (not shown in the figure) on the first storage area I and a second storage area II. 的 second groove (not marked in the figure).

[0069] The function of the mask layer 220 is that, on the one hand, it is used to subsequently define the positions of the first side wall and the second side wall; on the other hand, it is used to subsequently form the first side wall and the second side wall together. A storage structure and a second storage structure provide a mask.

[0070] The material of the mask layer 220 includes: silicon oxide, silicon nitride, silicon oxynitride, silicon oxynitride, silicon oxynitride, or silicon oxynitride.

[0071] In this embodiment, the material of the mask layer 220 is silicon nitride.

[0072] A photolithography process is used to form the mask layer 220 having the first groove and the second groove.

[0073] Please refer to Image 6 , A first side wall 231 is formed on the side wall surface of the first groove, a second side wall 232 is formed on the side wall surface of the second groove, and the first side wall 231 and the second side wall 232 are located The surface of the storage unit material film.

[0074] The functions of the first sidewall spacers 231 and the second sidewall spacers 232 are, on the one hand, as a part of the first storage structure and the second storage structure, respectively, and on the other hand, together with the mask layer 220 as a subsequent etching The mask of the memory cell material film.

[0075] The material of the first sidewall 231 and the second sidewall 232 is different from the material of the mask layer 220.

[0076] In this embodiment, the material of the first sidewall spacer 231 and the second sidewall spacer 232 is silicon oxide.

[0077] The method for forming the first sidewall spacer 231 and the second sidewall spacer 232 includes: forming a first sidewall material film (not shown in the figure) on the surface of the memory cell material film and the surface of the mask layer 220; and etching back The first sidewall material film until the surface of the memory cell material film is exposed, a first sidewall 231 is formed on the sidewall surface of the first groove, and a second sidewall is formed on the sidewall surface of the second groove 232.

[0078] Then, using the mask layer 220, the first sidewall spacers 231, and the second sidewall spacers 232 as masks, the memory cell material film is etched to form a first opening structure and a second opening structure in the memory cell material film. Two-opening structure, a first storage unit and a second storage unit are formed on the first storage area I, a third storage unit and a fourth storage unit are formed on the second storage area II, and the first opening The structure is located between the first storage unit and the second storage unit, and the second opening structure is located between the third storage unit and the fourth storage unit.

[0079] Specifically, in this embodiment, the first opening structure includes: a control gate electrode film 214 located on the first storage area I and a first opening in the control gate dielectric film 213, and a first opening located on the first storage area I The floating gate electrode film 212 and the third opening in the floating gate dielectric film 211. The second opening structure includes: a second opening located in the control gate electrode film 214 and the control gate dielectric film 213 on the second storage area II, and the floating gate electrode film 212 and floating gate located on the second storage area II. The fourth opening in the dielectric film 211.

[0080] In this embodiment, the first opening and the second opening are formed at the same time, and the third opening and the fourth opening are formed at the same time. For the specific process of forming the first opening structure and the second opening structure, please refer to Figure 7 to Figure 9.

[0081] Please refer to Figure 7 Etch the control gate electrode film 214 and the control gate dielectric film 213 with the mask layer 220, the first sidewall spacer 231 and the second sidewall spacer 232 as masks until the surface of the floating gate electrode film 212 is exposed, A first control gate structure 241 and a second control gate structure 242, and a first opening 251 located between the first control gate structure 241 and the second control gate structure 242 are formed on the first storage region I. A third control gate structure 243 and a fourth control gate structure 244, and a second opening 252 located between the third control gate structure 243 and the fourth control gate structure 244 are formed on the second storage region II.

[0082] The first opening 251 and the subsequently formed third opening together form a first opening structure for filling material to form a first word line grid, and the second opening 252 and the subsequently formed fourth opening together form a second opening structure , Used to fill material to form the second word line grid.

[0083] The process of etching the control gate electrode film 214 and the control gate dielectric film 213 includes one or a combination of a wet etching process and a dry etching process.

[0084] In this embodiment, the process of etching the control gate electrode film 214 and the control gate dielectric film 213 is anisotropic dry etching.

[0085] It should be noted that in this embodiment, the substrate 200 on both sides of the first storage area I and the second storage area II and the substrate 200 between the first storage area I and the second storage area II will be removed later. On the control gate electrode film 214 ( Image 6 Shown in) and control gate dielectric film 213 ( Image 6 Shown in), so that the finally formed first control gate structure 241 and the second control gate structure 242 are only located on the first storage region I, and the finally formed third control gate structure 243 and the fourth control gate structure 244 are only located on the On the second storage area II.

[0086] In this embodiment, after the first opening 251 and the second opening 252 are formed, and before the third opening and the fourth opening are subsequently formed, the method for forming the memory further includes: on the sidewall surface of the first opening 251 A first isolation structure is formed, and a second isolation structure is formed on the surface of the sidewall of the second opening 252. The specific process of forming the first isolation structure and the second isolation structure forms reference 8 to Picture 9.

[0087] Please refer to Figure 8 After forming the first opening 251 and the second opening 252, a first isolation layer is formed on the surface of the mask layer 220, the surface of the first sidewall 231, and the sidewall surface of the first opening 251 on the first storage area I 261. A second isolation layer 262 is formed on the surface of the mask layer 220 on the second storage area II, the sidewall surface of the second sidewall 232, and the sidewall surface of the second opening 252; on the sidewall of the first opening 251 A third isolation layer 263 is formed on the surface of the first isolation layer 261; a fourth isolation layer 264 is formed on the surface of the second isolation layer 262 on the sidewall of the second opening 252.

[0088] The first isolation layer 261 and the third isolation layer 263 constitute a first isolation structure, and the second isolation layer 262 and the fourth isolation layer 264 constitute a second isolation structure.

[0089] The first isolation structure is used to isolate the first control gate structure and the first word line gate formed subsequently, and the second isolation structure is used to isolate the second control gate structure and the second word line formed subsequently Isolation between wire grids.

[0090] Specifically, in this embodiment, the first isolation layer 261 is also located on the bottom surface of the first opening 251, and the second isolation layer 262 is also located on the bottom surface of the second opening 252, and is engraved in the subsequent process. Eclipse removal.

[0091] Please refer to Picture 9 After forming the first opening 251 and the second opening 252, using the mask layer 220, the first sidewall spacer 231, and the second sidewall spacer 232 as a mask, the floating gate electrode film 212 and the floating gate dielectric film are etched 211, until the surface of the substrate 200 is exposed, a first floating gate structure 271 and a second floating gate structure 272 are formed on the first storage region I, and located on the first floating gate structure 271 and the second floating gate The third opening 253 between the structures 272 forms a third floating gate structure 273 and a fourth floating gate structure 274 on the second storage region II, and is located in the third floating gate structure 273 and the fourth floating gate structure. The fourth opening 254 between the gate structures 274.

[0092] In this embodiment, the mask layer 220, the first sidewall spacer 231, the second sidewall spacer 232, the first isolation layer 261, the second isolation layer 262, the third isolation layer 263, and the fourth isolation layer 264 are The mask is etched, and the floating gate electrode film 212 and the floating gate dielectric film 211 exposed by the first opening 251 and the second opening 252 are etched.

[0093] The third opening 253 is located at the bottom of the first opening 251, and the fourth opening 254 is located at the bottom of the second opening 252.

[0094] The first opening 251 and the third opening 253 constitute a first opening structure, and the second opening 252 and the fourth opening 254 constitute a second opening structure.

[0095] It should be noted that in this embodiment, the substrate 200 on both sides of the first storage area I and the second storage area II and the substrate 200 between the first storage area I and the second storage area II will be removed later. The floating gate electrode film 212 and the floating gate dielectric film 211 are formed so that the first floating gate structure 271 and the second floating gate structure 272 are finally formed only on the first storage region I, and the third floating gate structure 273 is formed And the fourth floating gate structure 274 is only located on the second storage area II.

[0096] So far, the first floating gate structure 271 on the surface of the first storage region I and the first control gate structure 241 on the surface of the first floating gate structure 271 constitute a first memory cell (not shown in the figure); The second floating gate structure 272 on the surface of a storage area I and the second control gate structure 242 on the surface of the second floating gate structure 272 constitute a second memory cell (not shown in the figure); located in the second storage area II The third floating gate structure 273 on the surface and the third control gate structure 243 on the surface of the third floating gate structure 273 constitute a third memory cell (not shown in the figure); the fourth on the surface of the second memory region II The floating gate structure 274 and the fourth control gate structure 244 on the surface of the fourth floating gate structure 274 constitute a fourth memory cell (not shown in the figure).

[0097] The first memory cell is adjacent to a first drain region formed subsequently, and the second memory cell is adjacent to a source region formed subsequently.

[0098] The third storage unit is adjacent to a second drain region formed subsequently, and the fourth storage unit is adjacent to a source region formed subsequently.

[0099] It should be noted that since the memory cell material film is still located on the substrate 200 between the first storage area I and the second storage area II, the mask layer 220 covers the first storage area I and the second storage area II. The memory cell material film on the substrate 200 between; using the mask layer 220, the first sidewall spacer 231, and the second sidewall spacer 232 as a mask, etching the memory cell material film also includes: A sacrificial memory cell (not shown in the figure) is formed on the substrate 200 between the first storage area I and the second storage area II, and the sacrificial storage unit is located between the second storage unit and the fourth storage unit. The sacrificial memory cell will be removed, and a third opening structure will be formed between the second memory cell and the fourth memory cell.

[0100] Please refer to Picture 10 After forming the first opening structure and the second opening structure, a first word line grid 281 is formed in the first opening structure, and a second word line grid 282 is formed in the second opening structure.

[0101] The method for forming the first word line grid 281 and the second word line grid 282 includes: on the bottom and sidewall surfaces of the first opening structure and the second opening structure, and the first isolation structure and the second isolation structure surface A word line dielectric film (not shown in the figure) is formed; a word line electrode film (not shown in the figure) is formed on the surface of the word line dielectric film, and the word line electrode film fills the first opening structure and the first opening structure. Two opening structures; planarize the word line electrode film and the word line dielectric film until the first isolation structure and the second isolation structure are exposed, a first word line grid 281 is formed in the first opening structure, and the A second word line grid 282 is formed in the second opening structure.

[0102] The first word line gate 281 is located between the first memory cell and the second memory cell; the second word line gate 282 is located between the third memory cell and the fourth memory cell.

[0103] So far, the first storage structure includes: the first storage unit and the second storage unit on the first storage area I, and the first word line gate 281; the second storage structure includes: the second storage area II The upper third and fourth memory cells, and the second word line gate 282.

[0104] Then, the sacrificial memory cell and the mask layer 220 on the surface of the sacrificial memory cell are removed until the surface of the substrate 200 is exposed to form a third opening structure, and the third opening structure exposes the first sidewall 231 and the second sidewall The sidewall 232, the second storage unit and the sidewall surfaces of the fourth storage unit. Please refer to the specific process of forming the third opening structure Figure 11 to Figure 12.

[0105] Please refer to Picture 11 A patterned layer 285 is formed on the surface of the first word line grid 281, the surface of the second word line grid 282, the first isolation structure, and the surface of the second isolation structure, and the patterned layer 285 exposes the first storage region I And the surface of the mask layer 220 on the substrate 200 between the second storage area II.

[0106] The patterned layer 285 and the mask layer 220 have different materials.

[0107] The material of the patterned layer 285 includes hard mask material or photoresist.

[0108] In this embodiment, the material of the patterned layer 285 is silicon oxide.

[0109] Please refer to Picture 12 Using the patterned layer 285 as a mask, the mask layer 220 and the sacrificial memory cell located at the bottom of the mask layer 220 are etched until the surface of the substrate 200 is exposed to form the third opening structure 291.

[0110] The third opening structure 291 provides space for the subsequent formation of source lines.

[0111] The process of etching the mask layer 220 and the sacrificial memory cell located at the bottom of the mask layer 220 includes one or a combination of a wet etching process and a dry etching process.

[0112] The third opening structure 291 is located between the first storage structure and the second storage structure.

[0113] Please refer to Figure 13 After the third opening structure 291 is formed, ion doping is performed on the substrate 200 between the first storage region I and the second storage region II to form a source region (not shown in the figure).

[0114] In this embodiment, after forming the third opening structure 291 and before forming the source region, it further includes: forming a fifth sidewall (not shown in the figure) on the surface of the sidewall of the third opening structure 291.

[0115] The method for forming the source region includes: using the patterned layer 285 and the fifth sidewall spacer as a mask, ion doping the substrate 200 exposed at the bottom of the third opening structure 291 to form the source region.

[0116] The function of the fifth sidewall is that, on the one hand, it protects the sidewalls of the second storage unit and the fourth storage unit to avoid being affected by ion implantation; on the other hand, it protects the second storage unit and subsequent formation The source line of, and the fourth storage unit and the source line formed subsequently play an isolation role.

[0117] The method for forming the fifth sidewall includes: forming a second sidewall material film (not shown in the figure) on the bottom and sidewall surfaces of the third opening structure, as well as the surface of the first isolation structure and the second isolation structure ); Etching the second sidewall material film until the surface of the substrate 200 is exposed, forming a fifth sidewall on the sidewall surface of the third opening structure.

[0118] The material of the fifth sidewall spacer includes: silicon oxide, silicon nitride, silicon carbide nitride, silicon nitride boride, silicon oxynitride, or silicon oxynitride. In this embodiment, the material of the fifth sidewall spacer is silicon oxide.

[0119] Please refer to Figure 14 After forming the source region, a source line 292 is formed in the third opening structure 291, and the source line 292 is located between the first storage structure and the second storage structure.

[0120] The method for forming the source line 292 includes: forming a source line material film (not shown in the figure) on the surface of the third opening structure 291 and the patterned layer 285; and planarizing the source line material film until the pattern is exposed The surface of the chemical layer 285 forms a source line 292.

[0121] The material of the source line 292 includes polysilicon and metal. In this embodiment, the material of the source line 292 is polysilicon.

[0122] In this embodiment, after forming the source line 292, the method further includes: removing the patterned layer 285.

[0123] Please refer to Figure 15 After forming the source line 292, a protective layer 293 is formed on the surface of the first word line grid 281, the second word line grid 282, and the source line 292.

[0124] The protective layer 293 is used to protect the surfaces of the first word line grid 281, the second word line grid 282, and the source line 292, so as to avoid loss in the subsequent etching process.

[0125] In this embodiment, the formation process of the protective layer 293 is a thermal oxidation process, and the material of the protective layer 293 is silicon oxide.

[0126] After the source line 292 and the protective layer 293 are formed, a first drain region and a second drain region are formed in the substrate 200 on both sides of the first storage area I and the second storage area II.

[0127] In this embodiment, the remaining memory cell material films 220 located on both sides of the first storage area I and the second storage area II ( Image 6 The mask layer 220 on the surface of the memory cell material film is removed, thereby exposing the surface of the substrate 200 on both sides of the first storage area I and the second storage area II. Please refer to the specific process of forming the first drain region and the second drain region Figure 16 to Figure 17.

[0128] Please refer to Figure 16 After the protective layer 293 is formed, the memory cell material film on the substrate 200 on both sides of the first storage area I and the second storage area II is removed ( Image 6 Shown in), and a mask layer 220 on the surface of the memory cell material film, exposing the surface of the substrate 200.

[0129] The protective layer 293 can protect the surface of the first word line grid 281, the second word line grid 282 and the source line 292 during the process of etching the mask layer 220 and the memory cell material film.

[0130] Please refer to Figure 17 , The substrate 200 is ion-doped, and a first drain region (not shown in the figure) and a second drain region (not shown in the figure) are formed in the substrate 200 on both sides of the first storage region and the second storage region II. Not marked).

[0131] Specifically, using the protective layer 293 as a mask, ion implantation is performed on the exposed substrate 200 to form the first drain region and the second drain region.

[0132] In this embodiment, after exposing the surface of the substrate 200 on both sides of the first storage area I and the second storage area II, before forming the first drain area and the second drain area, the method for forming the memory is also Including: forming a third side wall (not shown in the figure) on the side wall surface of the first storage unit and the first side wall 231, and forming a fourth side on the side wall surface of the third storage unit and the second side wall 232 Wall (not marked in the picture).

[0133] The functions of the third side wall and the fourth side wall are that, on the one hand, the third side wall constitutes a first storage structure, and the fourth side wall constitutes a second storage structure, which has an isolation effect; on the other hand, , It protects the sidewalls of the first storage unit and the third storage unit to avoid the impact of ion implantation.

[0134] The materials of the third sidewall and the fourth sidewall include silicon oxide, silicon nitride, silicon oxynitride, silicon nitride boride, silicon oxynitride, or silicon oxynitride. In this embodiment, the third sidewall spacer and the fourth sidewall spacer have a silicon oxide-silicon nitride-silicon oxide three-layer structure.

[0135] So far, a first storage structure is finally formed on the first storage area I. The first storage structure includes: a first storage unit and a second storage unit, and a storage unit located between the first storage unit and the second storage unit. The first word line gate 281, the first sidewall spacer 231 respectively located on the top surface of the first memory cell and the second memory cell, and the sidewall surface on the side of the first memory cell and the first sidewall 231 adjacent to the first drain region The third sidewall; the second storage structure is finally formed on the second storage area II, the second storage structure includes: a third storage unit and a fourth storage unit, and located in the third storage unit and the fourth storage The second word line grid 282 between the cells, the second sidewall 232 located on the top surface of the third memory cell and the fourth memory cell, and the side of the third memory cell and the second sidewall 232 adjacent to the second drain region The fourth side wall of the side wall surface.

[0136] In this embodiment, after forming the third sidewall spacer and the fourth sidewall spacer and before subsequently forming the first plug and the second plug, the method for forming the memory further includes: removing the protective layer 293; A contact resistance layer (not shown in the figure) is formed on the surface of the first word line grid 281, the second word line grid 282, and the source line 292.

[0137] Please continue to refer Figure 17 After forming the first drain region, a first plug 294 is formed on the first drain region, and the first plug 294 is electrically connected to the first drain region; forming the second drain region After that, a second plug 295 is formed on the second drain region, and the second plug 295 is electrically connected to the second drain region.

[0138] The first plug 294 is used to electrically connect the first drain area to the peripheral circuit, and the second plug 295 is used to electrically connect the second drain area to the peripheral circuit.

[0139] Correspondingly, the embodiment of the present invention also provides a memory formed by the above method, please continue to refer to Figure 17 Including: a memory, characterized by comprising: a substrate 200 including a first storage area I and a second storage area II that are adjacent and separated; located in the first storage area I and the second storage area The source region (not labeled in the figure) in the substrate 200 between II; the first drain region (not labeled in the figure) and the second drain region (not labeled in the figure) in the substrate 200 located on both sides of the first storage region I and the second storage region II Drain area (not marked in the figure); a first storage structure located on the first storage area I, the first storage structure includes: a first storage unit and a second storage unit, and a first storage unit and a second storage unit A first word line gate 281 between two memory cells; a second memory structure located on the second memory area II, the second memory structure including: a third memory cell and a fourth memory cell, and a third memory cell The second word line grid 282 between the memory cell and the fourth memory cell.

[0140] The detailed description is given below in conjunction with the drawings.

[0141] The memory further includes: a source line 292 located on the source area and between the first storage structure and the second storage structure, and the source line 292 is electrically connected to the source area.

[0142] The memory further includes: a first plug 294 located on the first drain region, and the first plug 294 is electrically connected to the first drain region; a second plug 294 located on the second drain region A plug 295, and the second plug 295 is electrically connected to the second drain region.

[0143] The first storage unit is close to the first drain area; the second storage unit is close to the source area.

[0144] The third storage unit is close to the second drain area; the fourth storage unit is close to the source area.

[0145] The first memory cell includes: a first floating gate structure 271 located on a part of the surface of the first storage area I, and a first control gate structure 241 located on the surface of the first floating gate structure 271; the second memory The cell includes: a second floating gate structure 272 located on a part of the surface of the second storage region II, and a second control gate structure 242 located on the surface of the second floating gate structure 272.

[0146] The third storage unit includes: a third floating gate structure 273 located on a part of the surface of the second storage area II, and a third control gate structure 243 located on the surface of the third floating gate structure 273; the fourth storage The cell includes: a fourth floating gate structure 274 located on a part of the surface of the second storage region II, and a fourth control gate structure 244 located on the surface of the fourth floating gate structure 274.

[0147] The first storage structure further includes: first sidewall spacers 231 respectively located on the top surface of the first control gate structure 241 and the top surface of the second control gate structure 242; the second storage structure further includes: respectively located on the third control gate The top surface of the structure 243 and the second sidewall 232 on the top surface of the fourth control gate structure 244.

[0148] The first storage structure further includes: a third sidewall (not shown in the figure) on the sidewall surface of the first storage unit and the first sidewall 231 adjacent to the first drain region; the second storage structure also It includes: a fourth side wall (not shown in the figure) on the side wall surface of the third storage unit and the second side wall 232 adjacent to the second drain region.

[0149] The memory further includes: fifth sidewalls located on the sidewall surfaces on both sides of the source line 292, and the fifth sidewalls are respectively located between the source line 292 and the second storage unit, and between the source line 292 and the fourth storage unit. between.

[0150] Since the substrate 200 includes adjacent and separated first storage area I and second storage area II, the source area is located in the substrate 200 between the first storage area I and the second storage area II, the first drain area and the second storage area II The second drain area is located in the substrate 200 on both sides of the first storage structure and the second storage structure, so that the source area, the first drain area, and the first storage structure form a pair of memory cells, while the source area and the second drain area, And the second storage structure forms a pair of storage cells. In this way, on the one hand, the two pairs of storage cells share the source area, which is beneficial to reduce the distance between the two pairs of storage cells, thereby helping to increase the density of the memory; on the other hand, it is beneficial to The first drain region and the second drain region are jointly led out by one bit line, and one source line 292 leads out the source region. Through the reasonable layout of the memory cell array, the size of one active area period can be met, and only the size of one metal line period is required. , Thereby increasing the density of the memory cell array.

[0151] Figure 18 It is a schematic diagram of a memory cell array in an embodiment of the present invention.

[0152] Correspondingly, the present invention also provides a memory cell array, please refer to Figure 17 with 18 , Including: a substrate 200, the substrate 200 includes: a number of parallel and separate active regions 310 arranged along the second direction Y, and an isolation structure (not shown in the figure) surrounding the active region 310, the The source region 310 extends along the first direction X. In the first direction X, each active region 310 includes a number of memory cell regions, and each memory cell region includes adjacent and separated first and second memory regions I and Storage area II; a number of first drain regions (not shown in the figure) and second drain regions (not shown in the figure), and each first drain region and each second drain region are respectively located in the first storage In the substrate 200 on both sides of the area I and the second storage area II; several source areas (not shown in the figure), each source area is located in the substrate 200 between the first storage area I and the second storage area II; The first storage structure (not shown in the figure), each first storage structure is located on each first storage area I, the first storage structure includes: a first storage unit and a second storage unit, and located in the first storage unit The first word line grid between the memory cell and the second memory cell (not shown in the figure); a number of second memory structures, each second memory structure is located on each second memory area, the second memory structure Including: a third storage unit and a fourth storage unit, and a second word line grid (not shown in the figure) located between the third storage unit and the fourth storage unit; several source lines arranged in parallel along the first direction X 292. Each source line 292 is electrically connected to each source region; a plurality of bit lines 320 arranged in parallel along the second direction Y, and each bit line 320 is connected to the first drain region and the second drain region in the same column Electric connection.

[0153] It should be noted, Figure 17 for Figure 18 A schematic cross-sectional view along the A2-A3 tangent direction.

[0154] The memory cell array further includes: a plurality of first control lines 331 arranged in parallel along the first direction X, each of the first control lines 331 is electrically connected to the first memory cells in the same row; and a plurality of first control lines 331 are parallel along the first direction X Arranged second control lines 332, each of the second control lines 332 is electrically connected to the second memory cells in the same row; a plurality of third control lines 333 arranged in parallel along the first direction X, each of the third control lines Lines are electrically connected to the third storage cells in the same row; a plurality of fourth control lines 334 arranged in parallel along the first direction X, each of the fourth control lines is electrically connected to the fourth storage cells in the same row; The first word lines 341 arranged in parallel in the direction X, each first word line 341 is electrically connected to the first word line gate of the same row; a plurality of second word lines 342 arranged in parallel along the first direction X, each second word The line 342 is electrically connected to the second word line gate in the same row.

[0155] In this embodiment, in the first direction X, adjacent memory cell regions share the first drain region or the second drain region.

[0156] It should be noted that the column refers to the first direction X, and the row refers to the second direction Y.

[0157] Specifically, the first memory cell includes: a first floating gate structure 271 located on a part of the surface of the first storage area I, and a first control gate structure 241 located on the surface of the first floating gate structure 271; The second storage unit includes: a second floating gate structure 272 located on a part of the surface of the first storage area, and a second control gate structure 242 located on the surface of the second floating gate structure 272; the third storage unit includes: A third floating gate structure 273 located on a part of the surface of the second storage area II, and a third control gate structure 243 located on the surface of the third floating gate structure 273; the fourth storage unit includes: located in the second storage area The fourth floating gate structure 274 on the surface of part II and the fourth control gate structure 244 on the surface of the fourth floating gate structure 274.

[0158] Since each active area 310 includes several memory cell areas in the first direction X, and each memory cell area includes adjacent and separated first storage area I and second storage area II, each source area is located In the substrate 200 between the first storage area I and the second storage area II, each first drain area and each second drain area are respectively located in the substrate on both sides of the first storage area I and the second storage area II In 200, the source area, the first drain area, and the first storage structure form a pair of memory cells, while the source area, the second drain area, and the second storage structure form a pair of memory cells. In this way, on the one hand, two pairs The memory cells share the source region, which is beneficial to reduce the distance between the two pairs of memory cells, thereby helping to increase the density of the memory cell array; on the other hand, the first drain region and the second drain region are jointly led out by one bit line 320, one The source line 292 leads to the source area, and the bit line and the source line 292 are perpendicular to each other. By laying out metal lines in two directions, space is effectively utilized and reasonable layout is performed, so that the memory cell array can satisfy one active area. With the size of 310 cycles, only the size of one metal line cycle is required, thereby increasing the density of the memory cell array.

[0159] Correspondingly, the embodiment of the present invention also provides a driving method of the memory cell array, please continue to refer to Figure 18 , Including: providing the memory cell array described in any one of the above; determining the memory cell to be operated; applying a first voltage to the source line 292 connected to the source area of ​​the memory cell; The bit line 320 connected to the drain region and the second drain region applies a second voltage.

[0160] The driving method of the memory cell array further includes: applying a third voltage to the first word line 341 connected to the first word line of the memory cell; and applying a third voltage to the first word line 341 connected to the first memory cell of the memory cell. A fourth voltage is applied to the control line 331; a fifth voltage is applied to the second control line 332 connected to the second storage cell of the memory cell.

[0161] The following is attached Figure 17 with Figure 18 Give details.

[0162] When performing a read operation, the first voltage is less than the second voltage, the fourth voltage and the fifth voltage are not the same, the third voltage is less than or equal to the fourth voltage, and the third voltage is less than or equal to The fifth voltage.

[0163] Specifically, the first voltage ranges from 0V to 0.5V, the second voltage ranges from 0.5V to 1.2V, the third voltage ranges from 3V to 5V, and the fourth voltage ranges from 0V-6V, the range of the fifth voltage is 0V-6V.

[0164] Specifically, when the first memory cell is read, the fourth voltage is less than the fifth voltage; when the second memory cell is read, the fourth voltage is greater than the fifth voltage.

[0165] In this embodiment, the first voltage is 0V, the second voltage is 0.8V, the third voltage is 4.5V, the fourth voltage is 0V, and the fifth voltage is 4.5V. Under the condition of the pressurization, the third voltage is a positive voltage, which can form an inversion layer in the substrate 200 at the bottom of the first word line gate. At the same time, the voltage of the fifth voltage is higher, which can also cause the second storage An inversion layer is formed in the substrate 200 at the bottom of the cell. Therefore, whether the source region and the first drain region, or the source region and the second drain region are connected to form a current depends on the first floating gate structure 271, thereby The information in the first floating gate structure 271 in the first memory cell can be read.

[0166] In another embodiment, the first voltage is 0V, the second voltage is 0.8V, the third voltage is 4.5V, the fourth voltage is 4.5V, and the fifth voltage is 0V. Under the pressure, the information in the second floating gate structure 272 in the second memory cell can be read.

[0167] At the same time, the driving method of the memory cell array further includes: grounding the second word line 342 connected to the second word line gate of the memory cell; connecting the second word line 342 connected to the third memory cell of the memory cell The third control line 333 is grounded; the fourth control line 334 connected to the fourth storage unit of the memory cell is grounded. Because the second word line 342 is grounded, the channel at the bottom of the second word line gate in the memory cell to be operated cannot be turned on, so that the third memory cell and the fourth memory cell cannot be read.

[0168] When a write operation is performed, the first voltage and the second voltage are different, the fourth voltage and the fifth voltage are different, and the third voltage is smaller than the fourth voltage and the fifth voltage.

[0169] Specifically, the first voltage ranges from 0V to 7V, the second voltage ranges from 0V to 7V, the third voltage ranges from 0.5 to 2V, and the fourth voltage ranges from 4V to 10V. , The range of the fifth voltage is 4V-10V.

[0170] Specifically, when a write operation is performed on the first memory cell, the second voltage is greater than the first voltage, and the fourth voltage is greater than the fifth voltage; when a write operation is performed on the second memory cell, the The second voltage is less than the first voltage, and the fourth voltage is less than the fifth voltage.

[0171] In an embodiment, the first voltage is 0V, the second voltage is 5.5V, the third voltage is 1.5V, the fourth voltage is 8V, and the fifth voltage is 5V. Under the pressure condition, the third voltage is a positive voltage, which enables the formation of an inversion layer in the substrate 200 at the bottom of the first word line grid. The fourth voltage is a positive voltage, which can form an inversion layer in the substrate 200 at the bottom of the first memory cell. At the same time, the fifth voltage is a positive voltage, which can also cause an inversion layer to be formed in the substrate 200 at the bottom of the second memory cell. Therefore, a current can be conducted between the source region and the first drain region. In addition, the second voltage is much greater than the first voltage, so that the carriers in the channel have greater kinetic energy, so that a certain number of hot carriers will tunnel and enter the first float in the first memory cell. The gate structure 271, thereby completing the writing operation.

[0172] In another embodiment, the first voltage is 5.5V, the second voltage is 0V, the third voltage is 1.5V, the fourth voltage is 5V, and the fifth voltage is 8V. Under the pressure condition, a certain number of hot carriers can be tunneled into the second floating gate structure 272 in the second memory cell, thereby completing the write operation.

[0173] At the same time, the driving method of the memory cell array further includes: grounding the second word line 342 connected to the second word line gate of the memory cell; and connecting the third control line connected to the third memory cell 333 is grounded; the fourth control line 334 connected to the fourth storage unit of the memory unit is grounded. Since the second word line 342, the third control line 333, and the fourth control line 334 are grounded, the channel at the bottom of the second word line gate in the memory cell to be operated cannot be turned on, so that the third memory cell cannot be connected. And the fourth storage unit perform a write operation.

[0174] When the erase operation is performed, the first voltage and the second voltage are the same, the fourth voltage and the fifth voltage are the same, the third voltage is greater than the first voltage and the second voltage, and the fourth voltage and the second voltage are the same. The five voltage is less than the first voltage and the second voltage.

[0175] Specifically, the first voltage ranges from 0 to 0.5V, the second voltage ranges from 0 to 0.5V, the third voltage ranges from 8 to 12V, and the fourth voltage ranges from − 5V~-10V, the range of the fifth voltage is -5V~-10V.

[0176] In one embodiment, the first voltage is 0V, the second voltage is 0V, the third voltage is 8.5V, the fourth voltage is -7V, and the fifth voltage is -7V. Under the pressure condition, the third voltage is large enough to facilitate the tunneling of electrons in the first floating gate structure 271 and the second floating gate structure 272 located on both sides of the first word line gate 281 The first word line gate 281, at the same time, the fourth voltage and the fifth voltage are both negative voltages, which repel the electrons in the first floating gate structure 271 and the second floating gate structure 272, which further helps The electrons in the first floating gate structure 271 and the second floating gate structure 272 tunnel into the first word line gate 281, thereby simultaneously completing the erase operation on the first memory cell and the second memory cell.

[0177] At the same time, the driving method of the memory cell array further includes: grounding the second word line 342 connected to the second word line gate of the memory cell; connecting the second word line 342 connected to the third memory cell of the memory cell The third control line 333 is grounded; the fourth control line 334 connected to the fourth storage unit of the memory cell is grounded. Since the second word line 342, the third control line 333, and the fourth control line 334 are grounded, the gap between the third floating gate structure 273 and the second word line gate 282 and the fourth floating gate in the memory cell to be operated is There is no voltage difference between the gate structure 274 and the second word line gate 282, so that the third memory cell and the fourth memory cell cannot be erased.

[0178] Although the present invention is disclosed as above, the present invention is not limited to this. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be subject to the scope defined by the claims.